Abstract: A method for implementing an adder including receiving a first and second operand. A sum of one or more corresponding digits from the first operand and the second operand is calculated. The calculating is performed by a plurality of adder blocks. Output from the calculating includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The sums of the corresponding digits and the carry out indicators in a carry chain are stored in an intermediate result register. Each of the sums in the intermediate result register is incremented by one. A selection between each of the sums and the sums incremented by one is performed. Input to the selecting includes the carry chain, and the output from the selecting includes a final sum of the first operand and the second operand. The final sum is stored in an output register.

Abstract: A method for implementing an adder including receiving a first and second operand. A sum of one or more corresponding digits from the first operand and the second operand is calculated. The calculating is performed by a plurality of adder blocks. Output from the calculating includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The sums of the corresponding digits and the carry out indicators in a carry chain are stored in an intermediate result register. Each of the sums in the intermediate result register is incremented by one. A selection between each of the sums and the sums incremented by one is performed. Input to the selecting includes the carry chain, and the output from the selecting includes a final sum of the first operand and the second operand. The final sum is stored in an output register.

Abstract: A system for performing decimal floating point addition. The system includes input registers for inputting a first and second operand for an addition operation. The system also includes a plurality of adder blocks, each calculating a sum of one or more corresponding digits from the first operand and the second operand. Output from each of the adder blocks includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The calculating is performed during a first clock cycle. The system also includes an intermediate result register for storing the sums of the corresponding digits output from each of the plurality of adder blocks, the storing during the first clock cycle. The system further includes a carry chain for storing the carry out indicator output from each of the plurality of adder blocks, the storing occurring during the first clock cycle.

Abstract: The present invention relates to a method and system for determining the status of each entry in an instruction window buffer in multi-processor, parallel processing environments. A combinatorial circuit, which automatically generates active instruction window status information, is added to the buffer itself. This status information is used by a plurality of processes like renaming registers and issuing and committing instructions as an output associated with a respective buffer entry.

Abstract: The present invention relates to central processing units in computer systems, and in particular, it relates to a method and a respective hardware implementation of an add operation and a subtract operation. A combined add and subtract/compare logic is disclosed comprising: adding a less significant part of two add operands for generating a carry-out bit using a first carry network, adding a respective more significant part of the add operands for bit wise generating sum bits and carry bits, performing a combined subtract operation by bit wise operating a second carry network with respective bits of the more significant part of the subtract operand, and with respective ones of said sum bits, and said carry-out bit of said less significant part add operation, and the carry-out bits of said more significant part add operation. Speed is increased and chip area is saved.

Abstract: The present invention relates to central processing units in computer systems, and in particular, it relates to a method and a respective hardware implementation of an add operation and a subtract operation. A combined add and subtract/compare logic is disclosed comprising: adding a less significant part (50, 52) of two add operands (20, 22) for generating a carry-out bit (54) using a first carry network, adding a respective more significant part (51, 53) of the add operands (20, 22) for bit wise generating sum bits (56) and carry bits (58), performing a combined subtract operation by bit wise operating a second carry network with respective bits of the more significant part (55) of the subtract operand (24), and with respective ones of said sum bits (56), and said carry-out bit (54) of said less significant part (50, 52) add operation, and the carry-out bits (58) of said more significant part (51, 53) add operation. Speed is increased and chip area is saved.

Abstract: The present invention relates to storage devices in computer systems and in particular, it relates to an improved method and system for efficiently operating buffer memories. A considerable performance gain can be achieved by autonomous determination of relevant status information by the respective entry itself. This is done with combinatorial logic, preferably. A simple combinatorial circuit is added to the buffer itself which automatically generates the active window status information as required for the plurality of processes like renaming registers, issuing and committing instructions as an output associated with a respective buffer entry.