Abstract: A processor for character strings A, B of variable length serves for the fast detection of match, mismatch and comparative difference conditions between them. The character strings, whose lengths are delimited by character string termination marks, are split into consecutive substrings with a byte count corresponding to the data path width, and processed to detect a match, a mismatch and an end-of-byte mark. Each substring is routed via operand registers (16,18) in parallel to an arithmetic unit (20), a logic unit (22) and a comparator unit (24) and simultaneously processed. The arithmetic unit (20) subtracts one substring from the other substring, the logic unit (22) compares both substrings with each other and the comparator unit (24) compares the bytes of both substrings with the contents of a marking register (26), previously set to the end-of-string mark. These operations are executed in one machine cycle.

Abstract: A computer system is described with a 32 bit arithmetic and logic unit which is coupled to a 64 bit data bus. A number of general purpose registers are provided which have 32 bits each and which are organized in two groups. Two 32 bit data words which are present on the data bus can be transmitted and stored in the two groups of the general purpose registers. From there, the two data words can be transmitted via two operand registers to the arithmetic and logic unit. Several further lines are provided for bypassing the general purpose registers and/or the arithmetic and logic unit, if desired. Due to the fact that two data words can always be transmitted, the performance of the computer system is enhanced.