Abstract: During the transmission of digital signals which are interlaced in a multiplex signal, plesiochronic clock frequencies are also matched by means of positive-zero-negative stuffing. In this case, the time intervals of the phase changes can be large in comparison with the time constant of a phase low-pass filter which is formed by a phase-locked loop at the receiving end, which results in a jitter of approximately 1 UI. This jitter can be reduced if additional stuffing processes are inserted in pairs, in such a manner that an additional positive stuffing process (PST) is followed by such a negative stuffing process (NST) or, overall, vice versa, and if the time intervals within the pairs and/or between the pairs are selected in such a manner that the mean value of the phase difference between an incoming digital signal at the transmission end and an outgoing digital signal at the transmission end, which is contained in the multiplex signal, averaged over a specific time duration, remains approximately constant.

Abstract: In byte-wise stuffing of synchronous signals of the synchronous digital multiplex hierarchy, jitter which complicates timing recovery occurs with phase-jumps of 8 UI. A possibility is therefore sought of converting jitter into drift. This is achieved using a phase-locked loop (PLL) in which a phase-jump compensator (7) is inserted between the output (4) of a phase discriminator (3) and the input (5) of an oscillator (6). The phase-jump compensator converts an input correcting quantity (K.sub.e) into an output correcting quantity (K.sub.a). When no stuffing is being performed, the input correcting quantity (K.sub.e) leaves the phase-jump compensator (7) unchanged (a1, b1). If positive stuffing (+St) is being performed, the pulses, thereby lengthened, of the input correcting quantity (K.sub.e) are firstly shortened to the standard duration (x1) and subsequently lengthened in a stepwise fashion to the original duration (c1, d1).

Abstract: Method for inputting signals into and outputting signals out of subareas of the auxiliary signals of transport modules of a synchronous digital signal hierarchy.The invention is based on the object of specifying a method for outputting signals from at least one subarea of the auxiliary signals and for inputting signals into at least one subarea of the auxiliary signals of transport modules of a synchronous digital signal hierarchy according to the CCITT Draft Recommendations G.70X, G.70Y and G.70Z.This object is achieved during outputting in that a subarea of the auxiliary signals is output from the transport module (STM-4) in a demultiplexing and spreader means (1a) and is spread over a time span within the frame. The spread signal, for example, is resolved into the auxiliary signals (TB-STM-4) of the selected subarea that are allocated to the transport modules of the lowest hierarchy level contained in the transport module (STM-4).

Abstract: A method and apparatus for recovering the clock and/or the clock phase of a synchronous or plesiochronic digital signal provide that logic circuits in gate arrays or cell arrays recover the clock. In an auxiliary clock generator, an auxiliary clock is generated, or auxiliary clocks of the same frequency and different phase relationship extracted therefrom are generated which, conducted by way of a phase correction facility, provide an auxiliary data clock as the recovered clock. In principle, the frequency of the auxiliary clock or auxiliary clocks deviates from that of the auxiliary data clock to be formed. A phase sensor checks whether the active edges of the digital signal and of the auxiliary data clock have approached each other to less than a predetermined time interval and emits a corrections signal as soon as such an event occurs.

Abstract: In a switching location for TDM multiplexing of a combination of a plurality of channels for digital signals to form a common channel in one transmission direction and for demultiplexing a common transmission channel into a plurality of channels in the opposite transmission direction, the signals of the individual communications channels are combined to form pulse messages each of which is preceeded by a frame identifier word monitored by a monitoring memory with respect to its bit sequence and with respect to its periodicity. Double monitoring devices and one's density monitoring devices are provided for the input signals arriving via the individual communications channels. Potentially, code converter monitoring devices for the input and output signals are provided. A stepping bit monitoring device is provided for the input signals arriving via the individual communications channels. A level monitoring device is provided for the input signals arriving via the common communications channel.

Abstract: The invention relates to an electrical filter circuit operated with a definite sampling and clock frequency f.sub.T, such filter being made up of CTD elements, and having at least one bipolar or quadripolar resonator in the form of a self-contained conductor loop (for example, C.sub.1, C.sub.2) with unidirectional transmission behavior.Differences in the transfer capacitances of such circuits are reduced, as far as possible, in order to thereby simplify integrated manufacture as far as possible, by positioning the frequency band to be filtered out at a frequency position which lies above half the clock frequency (f.sub.T /2), or in the range from f.sub.T /2 through 3f.sub.T /2.

Abstract: A carrier frequency communication transmission system has a premodulation band above the transmission position of the base primary group of 60-108 kHz and utilizes mechanical filters as channel filters and also a common group filter in order to filter out the primary group band. Bending resonators having longitudinal coupling are utilized as the mechanical filters. The frequency range of the premodulation band at its lower limit is determined by a frequency spacing of at least 4 kHz from the upper band limit of the primary group band and the upper limit of the frequency range is determined in that the interfering natural oscillations, inasmuch as they occur in the lower stop band of the channel filter, lie at least 12 kHz below the lower limit of the primary group band. Highly stabilized piezo ceramics is used as the electromechanical transducer material.