Patents by Inventor Will Eatherton

Will Eatherton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-threaded packet processing architecture with global packet memory, packet recirculation, and coprocessor
    Patent number: 7551617
    Abstract: A network processor has numerous novel features including a multi-threaded processor array, a multi-pass processing model, and Global Packet Memory (GPM) with hardware managed packet storage. These unique features allow the network processor to perform high-touch packet processing at high data rates. The packet processor can also be coded using a stack-based high-level programming language, such as C or C++. This allows quicker and higher quality porting of software features into the network processor. Processor performance also does not severely drop off when additional processing features are added. For example, packets can be more intelligently processed by assigning processing elements to different bounded duration arrival processing tasks and variable duration main processing tasks. A recirculation path moves packets between the different arrival and main processing tasks.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: June 23, 2009
    Assignee: Cisco Technology, Inc.
    Inventors: Will Eatherton, Earl T. Cohen, John Andrew Fingerhut, Donald E. Steiss, John Williams
  • Multi-threaded packeting processing architecture
    Publication number: 20060179156
    Abstract: A network processor has numerous novel features including a multi-threaded processor array, a multi-pass processing model, and Global Packet Memory (GPM) with hardware managed packet storage. These unique features allow the network processor to perform high-touch packet processing at high data rates. The packet processor can also be coded using a stack-based high-level programming language, such as C or C++. This allows quicker and higher quality porting of software features into the network processor. Processor performance also does not severely drop off when additional processing features are added. For example, packets can be more intelligently processed by assigning processing elements to different bounded duration arrival processing tasks and variable duration main processing tasks. A recirculation path moves packets between the different arrival and main processing tasks.
    Type: Application
    Filed: February 8, 2005
    Publication date: August 10, 2006
    Applicant: Cisco Technology, Inc.
    Inventors: Will Eatherton, Earl Cohen, John Fingerhut, Donald Steiss, John Williams