Patents by Inventor Will Hsu

Will Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7971119
    Abstract: A method for defect-based scan analysis comprises, determining a neighborhood net for a circuit node, injecting defects into the neighborhood net, modeling the defects with stuck-at-0 and stuck-at-1 fault models, generating and applying test patterns to the neighborhood net, determining whether the injected defects are observable as faults, adding the test patterns to a set of effective test patterns if the defects are observable, mapping the test patterns to possible stuck-at-0 faults or stuck-at-1 faults, collecting stuck-at-0 and stuck-at-1 fault test patterns, performing stuck-at-0 and stuck-at-1 fault simulations using the stuck-at-0 and stuck-at-1 fault test patterns, respectively, generating first and second fault lists, combining first and second fault lists into combined fault lists, deriving a description of the combined fault lists using a complete set of fault models, filtering the combined fault lists to yield a collection of effective faults, and determining a defect for each of the effective fa
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: June 28, 2011
    Assignee: aiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Will Hsu
  • Publication number: 20070089001
    Abstract: A method for defect-based scan analysis comprises, for each node in a first circuit, determining its neighborhood net, injecting defects and modeling the defects with stuck-at-0 and stuck-at-1 fault models, generating at least one test pattern and applying the at least one test pattern to the neighborhood net with the injected defects, determining whether the injected defects are observable as faults, adding the test pattern to a set of effective test patterns in response to the defect is observable as a fault, mapping the test patterns in the set of effective test patterns to possible stuck-at-0 fault or stuck-at-1 fault and collecting stuck-at-0 fault test patterns and stuck-at-1 fault test patterns, performing stuck-at-0 fault simulation using the stuck-at-0 fault test patterns and generating a first fault list, performing stuck-at-1 fault simulation using the stuck-at-1 fault test patterns and generating a second fault list, combining the first and second fault lists and deriving a description of the comb
    Type: Application
    Filed: September 29, 2006
    Publication date: April 19, 2007
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Will Hsu