Patents by Inventor Will Kiang Wong
Will Kiang Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9899794Abstract: A optoelectronic package includes an inner package with a dielectric substrate having at least a first dielectric level with a photodetector (PD) die on a die attach area, first routing connecting a first contact to a first external bond pad (FEBP), and second routing connecting a second contact to a second external bond pad (SEBP). An outer package (OP) includes a ceramic substrate including a light source die on a base portion in direct line of sight with the PD including a first electrode and second electrode. A first wire bond connects the FEBP to a first terminal, a second wire bond connects the SEBP to a second terminal, a third wire bond connects the first electrode to a third terminal, and a fourth wire bond connects the second electrode to a fourth terminal.Type: GrantFiled: June 30, 2014Date of Patent: February 20, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Will Kiang Wong, Roozbeh Parsa, William French, Noboru Nakanishi
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Publication number: 20150380895Abstract: A optoelectronic package includes an inner package with a dielectric substrate having at least a first dielectric level with a photodetector (PD) die on a die attach area, first routing connecting a first contact to a first external bond pad (FEBP), and second routing connecting a second contact to a second external bond pad (SEBP). An outer package (OP) includes a ceramic substrate including a light source die on a base portion in direct line of sight with the PD including a first electrode and second electrode. A first wire bond connects the FEBP to a first terminal, a second wire bond connects the SEBP to a second terminal, a third wire bond connects the first electrode to a third terminal, and a fourth wire bond connects the second electrode to a fourth terminal.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Inventors: WILL KIANG WONG, ROOZBEH PARSA, WILLIAM FRENCH, NOBORU NAKANISHI
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Patent number: 8857047Abstract: An apparatus for incorporating a metallic foil into a semiconductor package includes a carrier embossed with a multiplicity of cavities. Each of the cavities define a pedestal recessed with the cavities which penetrate only partially through the thickness of the carrier. A metallic foil overlying a pattern with the pedestals in direct contact and help support the metallic foil with the metallic foil pressed into at least some of the cavities. In other embodiments, a gap is between the metallic foil and bottoms of the cavities in a substrate. Integrated circuit dice are attached to the foil. Each die is attached to the foil in a region of the foil overlying a portion of the at least one device area pattern. Bonding wires electrically connect the integrated circuit dice to the foil.Type: GrantFiled: September 18, 2012Date of Patent: October 14, 2014Assignee: Texas Instruments IncorporatedInventors: Jaime A. Bayan, Nghia Thuc Tu, Will Kiang Wong, David Chin
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Patent number: 8341828Abstract: The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.Type: GrantFiled: October 13, 2010Date of Patent: January 1, 2013Assignee: National Semiconductor CorporationInventors: Jaime A. Bayan, Nghia Thuc Tu, Will Kiang Wong, David Chin
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Publication number: 20110023293Abstract: The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.Type: ApplicationFiled: October 13, 2010Publication date: February 3, 2011Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Jaime A. BAYAN, Nghia Thuc TU, Will Kiang WONG, David CHIN
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Patent number: 7836586Abstract: The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.Type: GrantFiled: August 21, 2008Date of Patent: November 23, 2010Assignee: National Semiconductor CorporationInventors: Jaime A. Bayan, Nghia Thuc Tu, Will Kiang Wong, David Chin
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Publication number: 20100046188Abstract: The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.Type: ApplicationFiled: August 21, 2008Publication date: February 25, 2010Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Jaime A. BAYAN, Nghia Thuc TU, Will Kiang WONG, David CHIN