Abstract: Embodiments disclosed herein are directed to techniques aimed at managing interference in a 3D NAND memory with a split or multiple channel configuration. Specially, it addresses the issue of program interference, where a programmed memory cell experiences disturbance from another cell within a closely configured environment.

Abstract: The memory device includes an array of split-gate cells with first memory cells and second memory cells that can operate independently of one another and are arranged in first side-strings and second-side strings respectively. Control circuitry is configured to perform a sensing operation on a selected first memory cell to detect its threshold voltage. During the sensing operation, the control circuitry applies a reference voltage to the selected first memory cell, applies a first positive voltage to the second memory cells of a plurality of unselected word lines to partially turn on the second memory cells of the unselected word lines, and applies at least one pass voltage to the first memory cells of the unselected word lines to turn on the first memory cells of the unselected word lines. The control circuitry then conducts a current through the selected first memory cell to detect its threshold voltage.

Abstract: The memory device includes an array of split-gate cells with first memory cells and second memory cells that can operate independently of one another and are arranged in first side-strings and second-side strings respectively. Control circuitry is configured to perform a sensing operation on a selected first memory cell to detect its threshold voltage. During the sensing operation, the control circuitry applies a reference voltage to the selected first memory cell, applies a first positive voltage to the second memory cells of a plurality of unselected word lines to partially turn on the second memory cells of the unselected word lines, and applies at least one pass voltage to the first memory cells of the unselected word lines to turn on the first memory cells of the unselected word lines. The control circuitry then conducts a current through the selected first memory cell to detect its threshold voltage.

Abstract: A memory device includes memory blocks and control circuitry configured to perform an erase operation to selectively erase selected memory cells of the memory blocks, selectively perform an erase verify operation during or subsequent to the erase operation, and perform an erase verify skip operation in which one or more of the erase verify operations are skipped during the erase operation. To perform the erase verify skip operation, the control circuitry is configured to supply a first erase voltage pulse and supply a second erase voltage pulse subsequent to the first erase voltage pulse, the second erase voltage pulse has a greater magnitude than the first erase voltage pulse, and supplying the second erase voltage pulse includes transitioning from the first erase voltage pulse to the second erase voltage pulse without ramping downward between the first erase voltage pulse and the second erase voltage pulse.

Abstract: Apparatuses and techniques are described for programming memory cells with a reduced number of program pulses. A program operation includes a first, foggy program pass followed by a second, fine program pass. The number of program loops in the foggy program pass is minimized while providing relatively narrow Vth distributions for the foggy states. The program loops include one or more checkpoint program loops in which a program speed of the memory cells is determined through a read operation. In a next program loop, the fast-programming memory cells are inhibited from programming while the slow-programming memory cells are programmed with a reduced speed by applying a program speed-reducing bit line voltage. This brings the threshold voltage of the slow-programming memory cells into alignment with the threshold voltage of the fast-programming memory cells.

Abstract: Apparatuses and techniques are described for programming memory cells with a reduced number of program pulses. A program operation includes a first, foggy program pass followed by a second, fine program pass. The number of program loops in the foggy program pass is minimized while providing relatively narrow Vth distributions for the foggy states. The program loops include one or more checkpoint program loops in which a program speed of the memory cells is determined through a read operation. In a next program loop, the fast-programming memory cells are inhibited from programming while the slow-programming memory cells are programmed with a reduced speed by applying a program speed-reducing bit line voltage. This brings the threshold voltage of the slow-programming memory cells into alignment with the threshold voltage of the fast-programming memory cells.

Abstract: Polymer compositions having improved electromagnetic (EMI) shielding properties under high temperature are disclosed. The polymer compositions comprise a thermoplastic polymer, stainless steel fiber, and optionally one or more of glass fiber, a conductive filler, a second polymer, and other additives. The disclosed compositions maintain heat resistance and other mechanical properties under high temperatures.

Abstract: Polymer compositions having improved EMI retention after annealing at high temperatures are disclosed.