Abstract: An integrated circuit (IC) tester includes set of tester channels, each for carrying out a test activity at a separate terminal of an IC device under test (DUT) during each cycle of a test. Each tester channel includes a disk for storing several instruction sets, each including instructions and control data defining a separate test. To set up the tester for a test, a host computer sends a command to each channel identifying the instruction set to be used. Each channel then executes the instructions of the identified set during the test. Each channel also includes a high-speed instruction memory that can read out instructions at a higher rate than the disk. Before starting a test, each channel moves instructions covering high-speed portions of the test from the disk to the instruction memory. Thereafter, during those high-speed portions of the test in which instructions must be read out and executed at a high rate, each channel acquires those instructions from its instruction memory.

Abstract: An integrated circuit (IC) tester includes set of tester channels, each for carrying out a test activity at a separate terminal of an IC device under test (DUT) during each cycle of a test. The tester also includes a disk drive having a removable disk for reading out scan or programming data to the tester channels during a test. Each tester channel includes an instruction memory for storing a set of instructions, and each tester channel executes its stored instructions during the test. Some of the instructions include VECTOR data directly indicating a particular test activity the tester channel is to carry out at a DUT terminal during a next test cycle. Others of the instructions tell the tester channel to acquire a particular number (N) of serial data bits as they are read out of the disk drive and to carry out an activity during each of the next N test cycles indicated by a state of a corresponding one of the N serial data bits.