Abstract: A synchronous integrated circuit clock circuit is disclosed. The clock circuit (200) receives a system clock (CLKX) and in response thereto, generates an internal clock (CLKI) that is shifted forward in phase with respect to the system clock signal (CLKX). The amount by which the internal clock (CLKI) is shifted remains relatively constant over a range of system clock (CLKX) frequencies. The clock circuit (200) includes a measuring section (202) that measures the period of the system clock (CLKX), a logic section (204) that determines a delay value based upon the duration of the system clock (CLKX) period, and a generation section (206), that provides the internal clock signal (CLKI).