Abstract: A combination multiplier/shifter circuit (FIG. 2) can be used to implement an arithmetic or execution unit, using the multiplier/shifter to perform both multiplication operations and shift operations (such as for alignment or normalization). The arithmetic unit includes separate multiplier and adder channels. The multiplication channel includes a Multiplier/Shifter Circuit (10) with both multiplication and shift logic. The multiplication logic comprises an Adder Tree 12 with a rectangular aspect ratio (71.times.12) and Booth Recoder Logic 14, and implements conventional Booth recoded multiplication. The shift logic comprises Shift Control Logic 20 and Shift Extender Logic 32. For multiplication operations, redundant partial/final products MS1 and MS2 (sum and carry) are generated as the multiplication output, with conversion to nonredundant partial products, and the addition of partial products to obtain a final product, being performed in the adder channel.

Abstract: A method and apparatus for performing division is described which first comprises approximating the short reciprocal of the divisor. A reciprocal bias adjustment factor is added to the approximation and the correctly biased short reciprocal is multiplied by a predetermined number of the most significant bits of the dividend and the product is truncated to generate a first quotient digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits at least as large as the number of bits required for the divisor. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single quotient digit value, which is also determined to be the number of bits in the short reciprocal. The quotient digit value is multiplied by the full divisor and the exact product is subtracted from the dividend to yield an exact partial remainder.