Patents by Inventor Willard E. Conley

Willard E. Conley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9229051
    Abstract: An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: January 5, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Puneet Sharma, Matthew A. Thompson, Willard E. Conley
  • Publication number: 20140132315
    Abstract: An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 15, 2014
    Inventors: Puneet Sharma, Matthew A. Thompson, Willard E. Conley
  • Patent number: 8507187
    Abstract: A first photoresist is applied over an optically dense layer and lithographically patterned to form an array of first photoresist portions having a pitch near twice a minimum feature size. The pattern in the first photoresist portions, or a first pattern, is transferred into the ARC layer and partly into the optically dense layer. A second photoresist is applied and patterned into another array having a pitch near twice the minimum feature size and interlaced with the first pattern. The pattern in the second photoresist, or a second pattern, is transferred through the ARC portions and partly into the optically dense layer. The ARC portions are patterned with a composite pattern including the first pattern and the second pattern. The composite pattern is transferred through the optically dense layer and into the underlayer to form a sublithographic pattern in the underlayer.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: August 13, 2013
    Assignees: International Business Machines Corporation, Freescale Semiconductor, Inc.
    Inventors: Veeraraghavan S. Basker, Willard E. Conley, Steven J. Holmes, David V. Horak
  • Patent number: 8119334
    Abstract: Negative photoresist over an insulating layer is exposed to radiation according to a pattern for an opening in the insulating layer for filling conductive material. A post of the negative photoresist is left over the location where the opening in the insulating layer is to be formed. A developable hard mask is formed over the post by a spin-on process so that the hard mask over the post is much thinner than directly over the insulating layer. An etch back is performed to remove the hard mask from over the post so that the post of negative photoresist is thus exposed. The post is removed to form an opening in the hard mask. An etch is performed to form the opening in the insulating layer aligned to the opening in the hard mask. The opening in the insulating layer is filled with the conductive material.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: February 21, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Willard E. Conley
  • Patent number: 7883829
    Abstract: In one embodiment, a photoresist is lithographically patterned to form an array of patterned photoresist portions having a pitch near twice a minimum feature size. Fluorine-containing polymer spacers are formed on sidewalls of the patterned photoresist portions. The pattern of the fluorine-containing polymer spacers is transferred into an underlying layer to form a pattern having a sublithographic pitch. In another embodiment, a first pattern in a first photoresist is transferred into a first ARC layer underneath to form first ARC portions. A planarizing second optically dense layer, a second ARC layer, and a second photoresist are applied over the first ARC portions. A second pattern in the second photoresist is transferred into the second ARC layer to form second ARC portions. The combination of the first ARC portions and second ARC portions function as an etch mask to pattern an underlying layer with a composite pattern having a sublithographic pitch.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: February 8, 2011
    Assignees: International Business Machines Corporation, Freescale Semiconductors, Inc.
    Inventors: Steven J. Holmes, Xuefeng Hua, Willard E. Conley
  • Patent number: 7741221
    Abstract: A method for forming a semiconductor device includes providing a plurality of features in a layout, selecting critical features from the plurality of features, placing a first plurality of short-range dummy etch features in the layout at a first distance from the critical features to increase the feature density near the critical features, wherein each of the first plurality of short-range dummy etch features has a first width, removing at least one of the first plurality of short-range dummy etch features from the layout that will subsequently interfere with the electrical performance of at least one active feature so that a second plurality of short-range dummy etch features remains, and using the layout to pattern a layer on a semiconductor substrate.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: June 22, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ruiqi Tian, Willard E. Conley, Mehul D. Shroff
  • Publication number: 20100099255
    Abstract: A method includes forming an insulating layer over a substrate, forming a masking layer over the insulating layer, forming a developable bottom anti-reflective coating (BARC) over the masking layer, forming a first photo resist layer over the developable BARC, exposing and developing portions of both the first photo resist layer and the developable BARC to form a first set of openings in the developable BARC, forming a second photo resist layer over the first set of openings and the developable BARC, exposing and developing portions of both the second photo resist layer and the developable BARC to form a second set of openings in the developable BARC, and extending each opening in the first and second set of openings through the masking layer and the insulating layer.
    Type: Application
    Filed: October 20, 2008
    Publication date: April 22, 2010
    Inventors: Willard E. Conley, Massud Abubaker Aminpur, Cesar M. Garza
  • Publication number: 20100028801
    Abstract: In one embodiment, a photoresist is lithographically patterned to form an array of patterned photoresist portions having a pitch near twice a minimum feature size. Fluorine-containing polymer spacers are formed on sidewalls of the patterned photoresist portions. The pattern of the fluorine-containing polymer spacers is transferred into an underlying layer to form a pattern having a sublithographic pitch. In another embodiment, a first pattern in a first photoresist is transferred into a first ARC layer underneath to form first ARC portions. A planarizing second optically dense layer, a second ARC layer, and a second photoresist are applied over the first ARC portions. A second pattern in the second photoresist is transferred into the second ARC layer to form second ARC portions. The combination of the first ARC portions and second ARC portions function as an etch mask to pattern an underlying layer with a composite pattern having a sublithographic pitch.
    Type: Application
    Filed: August 1, 2008
    Publication date: February 4, 2010
    Applicants: International Businesss Machines Corporation, Freescale Semiconductor Inc.
    Inventors: Steven J. Holmes, Xuefeng Hua, Willard E. Conley
  • Publication number: 20100009131
    Abstract: A first photoresist is applied over an optically dense layer and lithographically patterned to form an array of first photoresist portions having a pitch near twice a minimum feature size. The pattern in the first photoresist portions, or a first pattern, is transferred into the ARC layer and partly into the optically dense layer. A second photoresist is applied and patterned into another array having a pitch near twice the minimum feature size and interlaced with the first pattern. The pattern in the second photoresist, or a second pattern, is transferred through the ARC portions and partly into the optically dense layer. The ARC portions are patterned with a composite pattern including the first pattern and the second pattern. The composite pattern is transferred through the optically dense layer and into the underlayer to form a sublithographic pattern in the underlayer.
    Type: Application
    Filed: July 9, 2008
    Publication date: January 14, 2010
    Applicants: International Business Machines Corporation, Freescale Semiconductor Inc.
    Inventors: Veeraraghavan S. Basker, Willard E. Conley, Steven J. Holmes, David V. Horak
  • Publication number: 20090325106
    Abstract: A semiconductor fabrication method that includes forming a patterned mask (62, 72) by spin coating a developable hard mask layer (32) and a resist layer (42) over a semiconductor substrate (4). Subsequently, the resist layer (42) is exposed and developed to form a patterned resist layer (62), where the development step also removes the underlying hard mask layer (32), thereby forming a patterned mask (62, 72) which defines a void or printed feature to expose a region (97) over the semiconductor substrate which may be implanted, etched or otherwise processed.
    Type: Application
    Filed: June 27, 2008
    Publication date: December 31, 2009
    Inventors: Willard E. Conley, Terry G. Sparks, William J. Taylor, JR.
  • Publication number: 20090274982
    Abstract: Negative photoresist over an insulating layer is exposed to radiation according to a pattern for an opening in the insulating layer for filling conductive material. A post of the negative photoresist is left over the location where the opening in the insulating layer is to be formed. A developable hard mask is formed over the post by a spin-on process so that the hard mask over the post is much thinner than directly over the insulating layer. An etch back is performed to remove the hard mask from over the post so that the post of negative photoresist is thus exposed. The post is removed to form an opening in the hard mask. An etch is performed to form the opening in the insulating layer aligned to the opening in the hard mask. The opening in the insulating layer is filled with the conductive material.
    Type: Application
    Filed: April 30, 2008
    Publication date: November 5, 2009
    Inventor: Willard E. Conley
  • Publication number: 20040248016
    Abstract: A method of designing and forming a reticle (404), as well as the manufacture of a semiconductor substrate (410) using the reticle, includes defining a first edge of a reticle layout file. The first edge corresponds to a reference feature (12,14). The method further includes using the reference feature to insert a subresolution assist feature (62,64) into the reticle layout file. The subresolution assist feature is at an angle (&thgr;) with respect to a line (82,84) containing the first edge, wherein the angle differs from 90 degrees. In one embodiment, the subresolution assist features can be manually or automatically inserted into the layout file after the locations of the assist features have been determined. The subresolution assist features are not patterned on the substrate, but assist in forming resist features of uniform dimension.
    Type: Application
    Filed: June 6, 2003
    Publication date: December 9, 2004
    Inventors: Kevin D. Lucas, Robert E. Boone, Russell L. Carter, Willard E. Conley
  • Patent number: 6300035
    Abstract: Photoresist compositions are provided comprising 1) a resin binder having photoacid-labile groups, 2) an acid generator and 3) a photospeed control agent. Photoresists of the invention exhibit good photospeed and can provide highly resolved relief images of small dimensions, including lines of sub-micron and sub-half micron dimensions with at least essentially vertical side walls. Methods are also provided that include control of photospeed of a photoresist composition of the invention.
    Type: Grant
    Filed: August 4, 1998
    Date of Patent: October 9, 2001
    Assignees: Shipley Company, L.L.C., International Business Machines Corporation
    Inventors: James W. Thackeray, Peter R. Hagerty, James F. Cameron, Wu-Song Huang, Ahmad D. Katnani, Willard E. Conley
  • Patent number: 6207353
    Abstract: A resist formulation minimizes blistering during reactive ion etching processes resulting in an increased amount of polymer by-product deposition. Such processes involve exciting a gaseous fluorocarbon etchant with sufficient energy to form a high-density plasma, and the use of an etchant having a carbon-to-fluorine ratio of at least 0.33. In addition to a conventional photoactive component, resists which minimize blistering under these conditions include a resin binder which is a terpolymer having: (a) units that contain acid-labile groups; (b) units that are free of reactive groups and hydroxyl groups; and (c) units that contribute to aqueous developability of the photoresist. After the photoresist is patterned on the silicon oxide layer and the high-density plasma is formed, the high-density plasma is introduced to the silicon oxide layer to etch at least one opening in the silicon oxide layer.
    Type: Grant
    Filed: December 10, 1997
    Date of Patent: March 27, 2001
    Assignee: International Business Machines Corporation
    Inventors: Michael D. Armacost, Willard E. Conley, Tina J. Cotler-Wagner, Ronald A. DellaGuardia, David M. Dobuzinsky, Michael L. Passow, William C. Wille
  • Patent number: 5322765
    Abstract: Dry developable top surface imageable photoresist compositions which comprise, in admixture, a film-forming aromatic polymer resin activated to electrophilic substitution, an acid catalyzable agent capable of being inserted into the aromatic polymer resin, and a radiation degradable acid generating compound and processes for generating positive tone resist images on substrates therewith.
    Type: Grant
    Filed: November 22, 1991
    Date of Patent: June 21, 1994
    Assignee: International Business Machines Corporation
    Inventors: Nicholas J. Clecak, Willard E. Conley, Ranee W.-L. Kwong, Leo L. Linehan, Scott A. MacDonald, Harbans S. Sachdev, Hubert Schlosser, Carlton G. Willson
  • Patent number: 5296332
    Abstract: High sensitivity, high contrast, heat-stable resist compositions for use in deep UV, i-line e-beam and x-ray lithography. These compositions comprise a film-forming polymer having aromatic rings activated for electrophilic substitution, an acid catalyzable crosslinking agent which forms a hydroxy-stabilized carbonium ion, and a photoacid generator. The compositions are aqueous base developable.
    Type: Grant
    Filed: November 22, 1991
    Date of Patent: March 22, 1994
    Assignee: International Business Machines Corporation
    Inventors: Harbans S. Sachdev, Willard E. Conley, Premlatha Jagannathan, Ahmad D. Katnani, Ranee W. Kwong, Leo L. Linehan, Steve S. Muira, Randolph J. Smith
  • Patent number: 5240812
    Abstract: A protective material for use as an overcoating film for acid catalyzed resist compositions comprising a polymeric film forming compound, the films of which are impermeable to vapors of organic and inorganic bases.
    Type: Grant
    Filed: November 18, 1991
    Date of Patent: August 31, 1993
    Assignee: International Business Machines Corporation
    Inventors: Willard E. Conley, Ranee W. Kwong, Richard J. Kvitek, Robert N. Lang, Christopher F. Lyons, Steve S. Miura, Wayne M. Moreau, Harbans S. Sachdev, Robert L. Wood
  • Patent number: 4939070
    Abstract: The present invention discloses particular lithographic polymeric materials and methods of using these materials, wherein the polymeric materials have acid labile or photolabile groups pendant to the polymer backbone. The polymeric materials are sufficiently transparent to deep UV radiation to permit deep UV imaging, can be used to produce resist structures having thermal stability at temperatures greater than about 160.degree. C., and are sufficiently resistant to excessive crosslinking when heated to temperatures ranging from about 160.degree. C. to about 250.degree. C. that they remain soluble in common lithographic developers and strippers.The present invention also discloses resists comprising substituted polyvinyl benzoates which, after imaging, exhibit unexpectedly high thermal stability, in terms of plastic flow.
    Type: Grant
    Filed: July 7, 1988
    Date of Patent: July 3, 1990
    Inventors: William R. Brunsvold, Ming-Fea Chow, Willard E. Conley, Dale M. Crockatt, Jean M. J. Frechet, George J. Hefferon, Hiroshi Ito, Nancy E. Iwamoto, Carlton G. Willson
  • Patent number: 4931379
    Abstract: The present invention relates to increasing the autodecomposition temperature of particular resists. The resists are comprised of structures having recurrent acid labile groups which are typically pendant to the polymeric backbone. The autodecomposition temperature of a resist is increased by selecting substituent sidechains on the acid labile group which exhibit increased stability. Sidechain structures which provide increased autodecomposition stability include secondary structures capable of forming secondary carbonium ion intermediates and having an available proton adjacent to the carbonium ion formed during cleavage. Moieties which can be used as the secondary sidechain structures include secondary alkyl, including both cyclic and alicyclic alkyl, substituted deactivated secondary benzyl, and 1-(deactivated heterocyclic) secondary alkyl.
    Type: Grant
    Filed: November 3, 1988
    Date of Patent: June 5, 1990
    Assignee: International Business Machines Corporation
    Inventors: William R. Brunsvold, Willard E. Conley, Dale M. Crockatt, Nancy E. Iwamoto
  • Patent number: 4828964
    Abstract: A composition for use in a process for the deposition of patterned thin metal films on integrated circuit substrates, the composition comprising an admixture of a thermoplastic polyimide resin and a coumarin dye dissolved in a substituted phenol solvent. Optionally a polar solvent having a boiling point greater than 160.degree. C. and a low boiling organic compound (70.degree.-150.degree. C.) may be incorporated in the composition.
    Type: Grant
    Filed: September 4, 1987
    Date of Patent: May 9, 1989
    Assignee: International Business Machines Corporation
    Inventors: William R. Brunsvold, Willard E. Conley, Scott L. Jacobs, George L. Mack, David P. Merritt, Ann M. Uptmor