Abstract: A system and method involve determining the airspeed of a vehicle using the propagation time of an acoustic signal from a transmitter located at one end of the vehicle to a receiver located at the other end of the vehicle. A digital representation of the acoustic signal is created and stored within non-volatile memory within the transmitter, then converted into an electrical signal which is filtered, amplified, and input into a transducer contained within the transmitter. The transducer radiates an acoustic signal toward the receiver, which receives and filters the acoustic signal, converts it into a digital signal, and processes the digital signal to determine the acoustic signal propagation time. The acoustic signal may have a continuous wave form, a duty cycle of about 100%, a peak to average amplitude ratio of less than about 2.5, and Fourier components of substantially equal amplitude and random phase.

Abstract: An apparatus and process makes it possible to quickly and accurately determine an equivalent for the radar cross section and range delay of a signal provided by a radar target simulator system. This calibration process considers the gain and delays associated with a radar target generator, the receive and transmit antennas associated with the generator, and the receive and transmit cables going to and from the generator to the receive and transmit antennas, respectively. Accurately determining gain and delay through the radar target simulator system permits the simulator to provide a well-calibrated radar cross section and range for radars it is testing and calibrating.

Abstract: An antenna integrates a planar structure, wideband compact design, permitg phasability, into a single structure. The antenna design makes it possible to implement the antenna throughout the entire electromagnetic spectrum with little or no need for impedance matching. The antenna comprises a plurality of exponential-spiral shaped antenna arms in which each of the arms has a radially inner and radially outer end and in which the radially inner ends are spaced rotationally about a common axis, and in which the arms are separated circumferentially from each other in proportion to their distance from the common axis. Each of the spiral antenna arms includes an antenna element having a sinuous portion that has amplitude and period characteristics that vary in proportion to their distance from said common axis. The antenna elements are selectively coupled to an antenna feed.

Abstract: The invention includes a data memory having sequentially stored N-bit words that are each a binary description of a time at which an event is to occur. Also stored is a K-bit word, associated with each N-bit word, that is a binary description of what the scheduled event is to be. The invention utilizes a free-running clock and clock circuitry to gauge when an event should occur. The clock circuitry tallies an N-bit description of running time. M-bits of the N-bit description of running time are specified by a single fast synchronous counter. The remaining N-M bits are specified by two slow counters each of N-M bit capacity. Because incrementation of slow counters creates count settling times that may significantly affect accurate event sequencing, the slow counters are alternately incremented and a multiplexer is used to switch to the counter that will provide a "steady state" count at a scheduled event time.

Abstract: A moving target simulator is provided for testing a wide variety of radars ithout the need for a direct connection between the simulator and the radar under test. The simulator accurately replicates the pulse width and amplitude of transmitted radar signals and provides a delay feature that permits simulated target scenarios to be presented to a radar under test. The simulator incorporates control features that allow Doppler frequency changes to be accounted for and that permit signal level changes to be made as in accordance with inverse 4th law distance-dependent target-return power variation.

Abstract: An uninterrupted event-time recorder enables high-precision measurements of the time-of-occurrence of randomly- and rapidly-occurring, digitally specified events such as the leading and/or trailing edges of asynchronous pulses. The lowest order binary digits of the recorder are constructed of high-speed synchronous integrated circuit counter devices. For an N-bit timer having M low-order bits, the highest order (N-M) bit counting is executed by two parallel (N-M)-bit slow-speed counters, one of which is incremented by the terminal count of the M-bit high-speed counter and the other which is incremented by the most significant bit (MSb) of the M-bit counter. The (N-M)-bit counters are read out through a multiplexer controlled by the MSb.

Abstract: An interference canceller for cancelling an interfering signal generated by n interfering source from a transmission link between an antenna and a receiver. The interference canceller derives a sample of the interfering signal from the interfering source and down converts the sample to an intermediate frequency. A computer controlled delay path and computer controlled amplitude and phase modulator interatively adjusts a cancellation signal that is injected into the transmission link between the antenna and receiver to maximize the amplitude match between the cancellation signal and the interfering signal, and anti-phase the cancellation signal with respect to the interfering signal.