Abstract: Systems and methods for cache-based compressed display data storage are provided. One system includes memory operable to store compressed display data, a processor comprising a processing core and a cache, a cache storage module operably coupled to the memory and the processor, wherein the cache storage module is to initiate a storage of at least a portion of the compressed display data in the cache in response to an indication that the processing core is in an inactive mode. One method comprises, in response to an indication that a processor is in an inactive mode, transferring compressed display data from a frame buffer in memory to a cache associated with the processor, obtaining a first compressed display data from the cache, and decompressing the first compressed display data to generate a first uncompressed display data.

Abstract: An apparatus and method are disclosed for providing higher radix redundant digit lookup tables for digital lookup table circuits. A compressed direct lookup table unit accesses a redundant digits lookup table that is capable of providing a high order part and a low order part that can be directly concatenated to form an output numeric value. The redundant digits lookup table of the invention is structured so that no output overflow exceptions are created. A redundant digits lookup table recoder capable of providing recoded output values directly to partial product generators of a multiplier unit is also disclosed.

Abstract: Methods for determining the square root, reciprocal square root, or reciprocal of a number performed by a processor of a computer system. The methods produce high precision estimates without using iterative steps. In addition, the methods taught herein utilize compressed tables for the coefficient terms A, B, and C from the quadratic expression Ax2+Bx+C, thus minimizing hardware requirements.

Abstract: An apparatus and method is disclosed for updating a status register in an out of order execution pipeline. In one embodiment a dispatch unit in a floating point unit sets a MRI bit flag that indicates that an instruction is the most recently issued instruction. The dispatch unit resets the MRI bit flag for all other instructions. Each execution stage of the execution pipeline keeps track of the MRI bit flag information for the instruction. A writeback unit updates the status register after the execution of the instruction that has its MRI bit flag set. The writeback unit does not update the status register for instructions that have their MRI bit flag reset. This allows the instruction to be identified that is the most recent instruction to enter the dispatch unit.

Abstract: A variable speed floating point unit comprising: 1) an execution pipeline comprising a plurality of execution stages capable of executing floating point operations in a series of sequential steps; and 2) a clock controller capable of receiving an input clock signal and generating a variable speed output clock signal capable of clocking the execution pipeline. The clock controller adjusts a speed of the variable speed output clock signal according to a level of queued opcodes waiting to be executed in the execution pipeline.

Abstract: A floating point unit comprising: 1) an execution pipeline comprising a plurality of execution stages for executing floating point operations in a series of sequential steps; and 2) a try-again reservation station for storing a plurality of instructions to be loaded into the execution pipeline. Detection of a denormal result in the execution pipeline causes the execution pipeline to store the denormal result in a register array associated with the floating point unit and causes the execution pipeline to store a denormal result instruction in the try-again reservation station. The try-again reservation station subsequently re-loads the denormal result instruction into the execution pipeline and the de-normal result instruction retrieves the denormal result from the register array for additional processing.

Abstract: An apparatus and method are disclosed for providing higher radix redundant digit lookup tables for digital lookup table circuits. A compressed direct lookup table unit accesses a redundant digits lookup table that is capable of providing a high order part and a low order part that can be directly concatenated to form an output numeric value. The redundant digits lookup table of the invention is structured so that no output overflow exceptions are created. A redundant digits lookup table recoder capable of providing recorded output values directly to partial product generators of a multiplier unit is also disclosed.

Abstract: A processing system having a CPU core and a cache transfers data between a first block of memory and a second block of memory that is preferably partitioned out of the cache as a non-cacheable scratchpad area and performs address calculations with protection and privilege checks without polluting the cache. Responsive to executing a predetermined instruction, the CPU core signals the cache to prevent caching data during transfer from system to scratchpad memory thereby reducing the number of bus turnarounds while maintaining byte granularity addressability.

Abstract: There is disclosed an apparatus for loading instructions into the instruction execution pipeline of a pipelined processor. The apparatus for loading instructions comprises: 1) an instruction loading circuit that loads instructions from a first instruction thread into the instruction execution pipeline; and 2) a branch instruction detection circuit that detects a branch instruction in the first instruction thread. In response to the branch instruction detection, the instruction loading circuit stops loading instructions from the first instruction thread into the instruction execution pipeline and begins loading instructions from a second instruction thread into the instruction execution pipeline.

Abstract: A preloadable floating point unit includes first and second preload registers that hold a next operand and a next top of array (TOA) for use with a next FPU instruction held in an instruction queue pending completion of the current FPU instruction.

Abstract: A processing system includes a graphics subsystem that directly renders raster data to system memory and moves bitmaps between locations within system memory with the graphics subsystem providing the data and a processor providing the virtual-to-physical addresses with privilege and protection check mechanisms.

Abstract: An arithmetic circuit 10 for performing prescaled division uses a rectangular multiplier 16 and accumulator 30 operable to calculate a short reciprocal and scaled dividend and divisor to enable the sequential iterative calculation of large radix quotient digits. Each quotient digit can be calculated using a single pass through the rectangular multiplier 16 and accumulator 30 and can be accumulated to form a full precision quotient in a quotient register 36.

Abstract: A method and apparatus for performing division is described which first comprises approximating the short reciprocal of the divisor. A reciprocal bias adjustment factor is added to the approximation and the correctly biased short reciprocal is multiplied by a predetermined number of the most significant bits of the dividend and the product is truncated to generate a first quotient digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits at least as large as the number of bits required for the divisor. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single quotient digit value, which is also determined to be the number of bits in the short reciprocal. The quotient digit value is multiplied by the full divisor and the exact product is subtracted from the dividend to yield an exact partial remainder.

Abstract: A multiplier system 12 is disclosed which provides for the negation of an operand stored in an operand register 14. When a negative operand must be loaded into a partial product generator 26, a carry bit is selectively generated in carry logic 44 and a selected bit or bits within the partial product is set to zero. During a subsequent pass through the multiplier system 12, a bit is added at a block 46 to provide for the addition of the required quantity for the negation of the operand.

Abstract: A rectangular array signed digit multiplier circuit 10 is disclosed which comprises a multiplier core (28). The circuit (10) comprises a C-latch (14), a D-latch (18), and A-latch (26), and a feedback latch (52) operable to store operands to be input into the multiplier core (28) through a MULTIPLIER INPUT, a multiplicand INPUT, an ADDER INPUT and a FEEDBACK INPUT, respectively. The product output by the multiplier core (28) may comprise the sum of the product of the values input through the MULTIPLIER INPUT and MULTIPLICAND INPUT and the ADDER and FEEDBACK INPUTS. The product is stored in a result latch (40) and may be used in subsequent passes through multiplier core (28) through the use of a data path coupling result latch (40) with feedback latch (52). Multiplier core (28) comprises a series connection of a times three adder level (56), a Booth recoder level (58), a partial product generator level (60), a level one adder level (62), a level two adder level (64) and a level three adder level (66).

Abstract: A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect raio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal.

Abstract: A rectangular array signed digit multiplier circuit (10) is disclosed which comprises a multiplier core (28). The circuit (10) comprises a C-latch (14), a D-latch (18), an A-latch (26), and a feedback latch (52) operable to store operands to be input into the multiplier core (28) through a MULTIPLIER INPUT, a multiplicand INPUT, and ADDER INPUT and a FEEDBACK INPUT, respectively, The product output by the multiplier core (28) may comprise the sum of the product of the values input through the MULTIPLIER INPUT and MULTIPLICAND INPUT and the ADDER and FEEDBACK INPUTS. The product is stored in a result latch (40) and may be used in subsequent passes through multiplier core (28) through the use of a data path coupling result latch (40) with feedback latch (52). Multiplier core (28) comprises a series connection of a times three adder level (56), a Booth recoder level (58), a partial product generator level (60), a level one adder level (62), a level two adder level (64) and a level three adder level (66).

Abstract: A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal.

Abstract: A microcomputer includes I/O ports and registers which are mapped in memory space along with RAM and ROM and in which hardware invisible to the programmer performs a bus arbitration sequence to acquire an external bus when an off-chip reference requires the bus; and in which memory space that is used for on-chip references is recovered for use in external memory by manipulating bits in the memory address.

Abstract: A method for approximating mathematical functions using polynomial expansions is implemented in a numeric processing system (10) which comprises a control and timing circuit (18), a microprogram store (20) and a multiplier circuit (34). The multiplier circuit (34) may comprise a rectangular aspect ratio multiplier circuit (40) having an additional ADDER INPUT to enable the repeated evaluation of first order polynomials to evaluate polynomial expansions associated with each mathematical function. A constant store (28) is used to store predetermined coefficients for the polynomial expansion associated with each mathematical functions function. The microprogram store (20) is used to store argument transformation routines, polynomial expansions and result transformation routines associated with each mathematical function. The questions raised in reexamination request No. 90/004,138, filed Feb.