Abstract: A clock compensation circuit is provided. The circuit comprises a clock synchronization circuit coupled to receive an input clock signal, wherein the clock synchronization circuit generates a master clock signal and produces a plurality of internal logic clock signals. The circuit further comprises a phase comparator coupled to receive one of the plurality of internal logic clock signals and a sample clock from an associated receiver, wherein the phase comparator generates a control signal based on a phase comparison between the sample clock and the one of the plurality of internal logic clock signals and a down converter channel coupled to receive each of the plurality of internal logic clock signals and the control signal and to pass data in phase with the sample clock using the internal logic clock signal based on the control signal.

Abstract: A digital down converter is provided. The digital down converter includes an input adapted to receive an input signal, a mixer circuit coupled to the input to down convert the input signal, and a decimation circuit, coupled to the mixer. The decimation circuit is adapted to decimate the down converted signal by a factor selected based on a characteristic of the input signal. The digital down converter further includes a signal conditioning circuit, coupled to the output of the decimation circuit, that conditions the decimated signal, an interpolator, coupled to the decimation circuit, that increases the number of samples in the conditioned signal, and a second mixer circuit, coupled to the interpolator, the second mixer circuit adapted to modulate a carrier with the conditioned signal.

Abstract: A clock compensation circuit is provided. The circuit comprises a clock synchronization circuit coupled to receive an input clock signal, wherein the clock synchronization circuit generates a master clock signal and produces a plurality of internal logic clock signals. The circuit further comprises a phase comparator coupled to receive one of the plurality of internal logic clock signals and a sample clock from an associated receiver, wherein the phase comparator generates a control signal based on a phase comparison between the sample clock and the one of the plurality of internal logic clock signals and a down converter channel coupled to receive each of the plurality of internal logic clock signals and the control signal and to pass data in phase with the sample clock using the internal logic clock signal based on the control signal.

Abstract: A spectrum analyzer is provided. The spectrum analyzer includes an input adapted to receive an input signal and a mixer, coupled to the input. The mixer is adapted to produce a down converted signal from the input signal. The spectrum analyzer further includes an adjustable decimation circuit, coupled to the mixer, that selectively decimates the down converted signal, a decoder, coupled to the adjustable decimation circuit, that measures power in the decimated signal, and a control circuit, coupled to the mixer, that selectively controls the frequency of the down converted signals from the mixer to measure power over a frequency spectrum of the input signal.

Abstract: A circuit for receiving and decoding Manchester-encoded communication signals such as those used in an Ethernet network. The circuit uses a single local reference clock signal to clock a shift register that temporarily stores samples of the incoming signal. A window pointer selects a particular bit of the shift register as the current output bit; the value of the window pointer is maintained by a feedback loop which tracks any phase error in the incoming signal, that the output data remains in phase with the incoming signal. The combined functions of a Manchester-decoder and retiming circuit are thus provided in a simple circuit.

Abstract: A computer graphics technique for rendering shaded areas by using pseudo-random noise localized to image boundaries is disclosed. Calculated pixel values are initially generated using an arithmetic accuracy larger than the word size of an associated bitmap memory. The calculated pixel values thus have a most significant portion, corresponding to the portion which is to be stored in bitmap memory, and a least significant portion, corresponding to the additional accuracy. Pseudo-random noise, preferably generated by a linear feedback shift register, is then added to some or all of the least significant portion, and the carry output from this operation is added to the most significant portion. The most significant portion is then written into bitmap memory. Changes in the value of the integer portion thus occur with increased frequency as the distance to an intensity boundary decreases, since the random noise causes the dithering to occur with increased frequency.

Abstract: Automatic tracking of the topology of an extended local area network by augmenting a station address list kept by a bridge with a list of repeater numbers and repeater port numbers. The bridge periodically iterates through its list of stations to select a station address. The selected address table is forwarded to all of the repeaters connected to the bridge. The repeaters watch for the selected address appearing as a source address in a message on one of their ports. If the address is seen, they report the repeater port number back to the bridge. Because the repeaters are interconnected such that a predetermined port number is always used as the common port between repeaters, any possible ambiguities are eliminated.

Abstract: Method and apparatus for rendering a smooth-shaded graphics primitive vertical series of horizontal pixel spans which extend between beginning and trailing edges of the primitive, the pixel locations being spaced from each other by selected distances dX and dY. The apparatus produces X and Y addresses of the first and last pixels in the beginning span of the primitive and the number of spans in the primitive. Also produced are step values (dX/dY) indicating the slopes of the beginning and trailing edges, and a beginning intensity value for the first pixel in the beginning span. DX is added to the X address of each pixel in each span to determine the X address of the next pixel in that span and one of the step values is added to the X address of the first pixel in each span to calculate the X address of the first pixel in the next span of the primitive.