Abstract: A semiconductor device comprises a monocrystalline silicon wafer having a major surface lying in the <100> crystal plane. Disposed on the surface is a mesa having a generally square cross-section with generally rounded corners. The mesa has four main side walls each having a slope of around 45 degrees with respect to the base plane of the mesa, and the horizontal edges of the main side walls are disposed at an angle of at least around 12 degrees to the <110> directions on the wafer surface. The corners of the mesa each comprises a number of surfaces also having slopes of around 45 degrees and one surface having a slope of around 54 degrees. A high-low (N.sup.+ N.sup.- or P.sup.+ P.sup.-) junction is disposed within the mesa and makes a continuous line intercept with the mesa side walls around the entire periphery of the mesa. Except for exceptionally small deviations of no great significance, the high low junction intercept is at a constant height location entirely around the mesa periphery.

Abstract: A semiconductor integrated circuit device which may be utilized as a Darlington circuit having an input stage and an output stage is disclosed. The Darlington may be characterized as having an increased isolation between the input stage and the output stage.

Abstract: Two conductors are in resistive contact in spaced apart relation with a body of semiconductor material, e.g., silicon of P type conductivity, which is relatively lightly doped at the areas of contact, the electrical resistance at the areas of contact decreasing with increasing temperature. In one embodiment, portions of the conductors contact spaced apart regions of the body which are relatively highly doped at the areas of contact, parallel paths for current having different resistance characteristics thus being provided through the body between the conductors.

Abstract: To lower the resistance to current flow from, e.g., the base region to the base terminal lead, a channel of a conductivity type opposite to that of the base region, and of higher conductance, is disposed within the base region underlying the metal layer contact on the surface of the device. The metal layer contacts both the base region and the channel to electrically short the PN junction therebetween.

Abstract: In devices including a body of semiconductor material having layers of solder on a surface thereof serving as current connectors, flow of solder from the layers to terminal leads soldered to the layers during the terminal lead soldering process is prevented by the presence of a gap between the terminal leads and the solder layers. Electrical connection between the solder layers and the terminal leads is provided by conductive regions within the body to which the terminal leads and the solder layers are contacted.

Abstract: Regions of high resistivity, with respect to the surrounding material, are designed into a semiconductor device at points where hot-spots have been observed. A device made in this manner has very good second breakdown characteristics. One application is in large area junction transistors having an interdigitated base-emitter configuration.