Abstract: Apparatus (40) comprising a voltage input (49) for applying an unfiltered voltage (V_unfil) and a current input (48) for receiving a bias current (Ib) from a current source. The apparatus (40) further comprises a differential filtering resistive circuit with a first current mirror (44) and a second current mirror (43), being situated between a common output node (50) and said voltage input (49). A first mirror circuit (42) for mirroring the bias current (Ib) to said first current mirror (44), and a second mirror circuit (41) for mirroring a current (Ix) to said second current mirror (43) are employed. A filter capacitor (51) situated at the output side of the apparatus (40), said filter capacitor (51) being connected on one side to said common output node (50) and on the other side to ground. The apparatus (40) provides a filtered output voltage (V_fil) at said common output node (50).

Abstract: Apparatus (40) comprising a voltage input (49) for applying an unfiltered voltage (V_unfil) and a current input (48) for receiving a bias current (Ib) from a current source. The apparatus (40) further comprises a differential filtering resistive circuit with a first current mirror (44) and a second current mirror (43), being situated between a common output node (50) and said voltage input (49). A first mirror circuit (42) for mirroring the bias current (Ib) to said first current mirror (44), and a second mirror circuit (41) for mirroring a current (Ix) to said second current mirror (43) are employed. A filter capacitor (51) situated at the output side of the apparatus (40), said filter capacitor (51) being connected on one side to said common output node (50) and on the other side to ground. The apparatus (40) provides a filtered output voltage (V_fil) at said common output node (50).

Abstract: Apparatus (10) comprising a level shifter (15) connectable to a signal input (1) for receiving an input signal (s(t)) with a negative signal swing. The level shifter (15) provides for a DC shift of the input signal (s(t)) to provide an output signal (r(t)) with positive signal swing. The level shifter (15) comprises an amplifier (17) with a first input (11), a second input (12), and an output (13). A first capacitor (C1), a second capacitor (C2), a reference voltage supply (16), and a transistor (14; 74) serving as a switch, are arranged in a network as follows: the first capacitor (C1) is arranged between the signal input (1) and the first input (11), the second capacitor (C2) is arranged in a feedback-loop (18) between the output (13) and the first input (11), and the reference voltage supply (16) is connected to the second input (12). The transistor (14) is arranged in a branch (19) that bridges the second capacitor (C2), whereby a control signal (CNTRL) is applicable to a gate (14.

Abstract: Summarizing, the present invention provides an IVC (100), comprising an operational amplifier (110) with an inverting input (112) and an output (113), and a feedback resistor ladder network (120) coupled between the output (113) and the inverting input (112). The feedback resistor ladder network (120) comprises a main chain (121) composed of a plurality of substantially identical unit resistors (RU) connected in series, and a plurality of branches (124i), each branch (124i) coupling a node (Xi) in the main chain (121) to the inverting input (112) of the operational amplifier (110), each branch (124i) comprising a selectable feedback switch (123i). Further, some of the branches (124i) comprise a non-unit resistor (RNUi) coupled in series with the corresponding selectable feedback switch (123i). Further, the present invention provides a circuit comprising a FIRDAC (20) and a bias block (30) for providing at least one bias current for the FIRDAC (20).

Abstract: A FIRDAC (20) is described, coupled to a noise-shaper (12) with a DC offset. The resulting offset of the FIRDAC itself is compensated by a compensation current source (Pcomp; Ncomp) which is continuously ON. The FIRDAC has a plurality of FIRDAC cells (40), each cell comprising at least one current source (50; 70). In a FIRDAC cell having a relatively small current source, a dummy transistor (80; 90) is formed in the free space. The compensation current source is formed as a parallel combination of certain dummy transistors. In a possible embodiment, each FIRDAC cell (40) comprises a stack comprising a D-flipflop (60), a PMOS current mirror (50) above the flipflop, and an NMOS current mirror (70) below the flipflop. In a cell with relatively small PMOS and NMOS current mirrors, a dummy current mirrors (80; 90) are formed in the substrate (100). A plurality of these dummy current mirrors (90; 80) are connected in parallel to constitute said compensation current source (Ncomp, Pcomp). FIG. 4.

Abstract: A FIRDAC (20) is described, coupled to a noise-shaper (12) with a DC offset. The resulting offset of the FIRDAC itself is compensated by a compensation current source (Pcomp; Ncomp) which is continuously ON.

Abstract: A FIRDAC (20) is described, coupled to a noise-shaper (12) with a DC offset. The resulting offset of the FIRDAC itself is compensated by a compensation current source (Pcomp; Ncomp) which is continuously ON. The FIRDAC has a plurality of FIRDAC cells (40), each cell comprising at least one current source (50; 70). In a FIRDAC cell having a relatively small current source, a dummy transistor (80; 90) is formed in the free space. The compensation current source is formed as a parallel combination of certain dummy transistors. In a possible embodiment, each FIRDAC cell(40) comprises a stack comprising a D-flipflop (60), a PMOS current mirror (50) above the flipflop, and an NMOS current mirror (70) below the flipflop. In a cell with relatively small PMOS and NMOS current mirrors, a dummy current mirrors (80; 90) are formed in the substrate (100). A plurality of these dummy current mirrors (90; 80) are connected in parallel to constitute said compensation current source (Ncomp, Pcomp).

Abstract: Summarizing, the present invention provides an IVC (100), comprising an operational amplifier (110) with an inverting input (112) and an output (113), and a feedback resistor ladder network (120) coupled between the output (113) and the inverting input (112). The feedback resistor ladder network (120) comprises a main chain (121) composed of a plurality of substantially identical unit resistors (RU) connected in series, and a plurality of branches (124i), each branch (124i) coupling a node (Xi) in the main chain (121) to the inverting input (112) of the operational amplifier (110), each branch (124i) comprising a selectable feedback switch (123i). Further, some of the branches (124i) comprise a non-unit resistor (RNUi) coupled in series with the corresponding selectable feedback switch (123i).

Abstract: Apparatus for producing internal vertical sync signals from a source of standard and nonstandard rate external vertical signals. The apparatus includes a counting and reset arrangement for generating internal vertical sync signals in synchronization with the external vertical signals when the external signals are occurring at a standard rate. A nonstandard signal sampling arrangement causes the generation of the internal vertical sync signals in synchronization with the external signals at a nonstandard rate after a predetermined time in which these nonstandard signals occur. Still other circuit elements generate standard rate internal vertical sync signals during the predetermined time in which these nonstandard rate signals occur.

Abstract: An average beam current limiter for a kinescope responsive to video signals coupled to the kinescope via a signal transmission channel comprises a source of control signals representative of average current drawn by the kinescope. When average beam current exceeds a predetermined threshold level by an amount within a first range of beam current, a corresponding control signal is coupled to the signal transmission channel to vary the D.C. content of the video signal in a direction to limit beam current above the threshold level within the first range. When beam current exceeds the threshold level by a relatively greater amount within a second range of current, a corresponding control signal serves to vary the peak amplitude of the video signal to limit beam current within the second range.

Abstract: A controlled oscillator comprises an amplifier including an active device, a filter network arranged in a feedback loop of the amplifier for providing regenerative feedback to sustain oscillation of the amplifier, and a source of control signals. A common load network is provided for oscillatory signals produced by the amplifier and for the control signals, and is coupled to the filter network. The common load network comprises amplifying means having a low input impedance relative to an impedance presented to the oscillatory and control signals by parasitic capacitances which may be associated with respective output terminals of the active device and the source of control signals.