Patents by Inventor Willem-Jan Toren
Willem-Jan Toren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9570581Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.Type: GrantFiled: April 5, 2016Date of Patent: February 14, 2017Assignee: Silicon Storage Technology, Inc.Inventors: Willem-Jan Toren, Xian Liu, Gerhard Metzger-Brueckl, Nhan Do, Stephan Wege, Nadia Miridi, Chieng-Sheng Su, Cecile Bernardi, Liz Cuevas, Florence Guyot, Yueh-Hsin Chen, Henry Om'mani, Mandana Tadayoni
-
Publication number: 20160225878Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.Type: ApplicationFiled: April 5, 2016Publication date: August 4, 2016Inventors: Willem-Jan Toren, Xian Liu, Gerhard Metzger-Brueckl, Nhan Do, Stephan Wege, Nadia Miridi, Chieng-Sheng Su, Cecile Bernardi, Liz Cuevas, Florence Guyot, Yueh-Hsin Chen, Henry Om'mani, Mandana Tadayoni
-
Patent number: 9330922Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.Type: GrantFiled: March 7, 2012Date of Patent: May 3, 2016Assignee: Silicon Storage Technology, Inc.Inventors: Willem-Jan Toren, Xian Liu, Gerhard Metzger-Brueckl, Nhan Do, Stephan Wege, Nadia Miridi, Chien-Sheng Su, Cecile Bernardi, Liz Cuevas, Florence Guyot, Yueh-Hsin Chen, Henry Om'mani, Mandana Tadayoni
-
Patent number: 8729629Abstract: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.Type: GrantFiled: June 29, 2012Date of Patent: May 20, 2014Assignees: Atmel Rousset S.A.S., Laas-CNRSInventors: Willem-Jan Toren, Bruno Villard, Elsa Hugonnard-Bruyere, Gaetan Toulon, Frederic Morancho, Ignasi Cortes Mayol, Thierry Pedron
-
Patent number: 8686481Abstract: Disclosed are embodiments of a semiconductor device comprising a semiconductor body with a semiconductor image sensor comprising a two-dimensional matrix of picture elements, each picture element comprising a radiation-sensitive element coupled to MOS field effect transistors for reading the radiation-sensitive elements, wherein a semiconductor region is sunken in the surface of the body having the same conductivity type as the body and having an increased doping concentration, the semiconductor region being disposed between the radiation-sensitive elements of neighboring picture elements.Type: GrantFiled: April 26, 2006Date of Patent: April 1, 2014Assignee: TrixellInventors: Joris Pieter Valentijn Maas, Willem-Jan Toren, Hein Otto Folkerts, Willem Hendrik Maes, Willem Hoekstra, Daniel Wilhelmus Elisabeth Verbugt, Daniel Hendrik Jan Maria Hermes
-
Publication number: 20130234223Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.Type: ApplicationFiled: March 7, 2012Publication date: September 12, 2013Inventors: Willem-Jan Toren, Xian Liu, Gerhard Metzger-Brueckl, Nhan Do, Stephan Wege, Nadia Miridi, Chien-Sheng Su, Cecile Bernardi, Liz Cuevas, Florence Guyot, Yueh-Hsin Chen, Henry Om'mani, Mandana Tadayoni
-
Publication number: 20120267717Abstract: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.Type: ApplicationFiled: June 29, 2012Publication date: October 25, 2012Applicants: LAAS-CNRS, ATMEL ROUSSET SASInventors: Willem-Jan Toren, Bruno Villard, Elsa Hugonnard-Bruyere, Gaetan Toulon, Frederic Morancho, Ignasi Cortes Mayol, Thierry Pedron
-
Patent number: 8217452Abstract: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.Type: GrantFiled: August 5, 2010Date of Patent: July 10, 2012Assignees: Atmel Rousset S.A.S., LAAS-CNREInventors: Willem-Jan Toren, Bruno Villard, Elsa Hugonnard-Bruyere, Gaetan Toulon, Frederic Morancho, Ignasi Cortes Mayol, Thierry Pedron
-
Publication number: 20120032262Abstract: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.Type: ApplicationFiled: August 5, 2010Publication date: February 9, 2012Applicants: LAAS-CNRS, ATMEL ROUSSET SASInventors: Willem-Jan Toren, Bruno Villard, Elsa Hugonnard-Bruyere, Gaetan Toulon, Frederic Morancho, Ignasi Cortes Mayol, Thierry Pedron
-
Publication number: 20080197386Abstract: The invention relates to a semiconductor device with a semiconductor body (12) with an image sensor comprising a two-dimensional matrix of pixels (1) each comprising a radiation-sensitive element (2) with a charge accumulating semiconductor region (2A) and coupled to a number of MOS field effect transistors (3), in which in the semiconductor body (12) an isolation region (4) is sunken for the separation of neighboring pixels (1) underneath which a further semiconductor region (5) with an enlarged doping concentration is formed. According to the invention the further semiconductor region (5) is sunken in the surface of the semiconductor body (12) and wider than the isolation region (4).Type: ApplicationFiled: April 26, 2006Publication date: August 21, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.Inventors: Joris Pieter Valentijn Maas, Willem-Jan Toren, Hein Otto Folkerts, Willem Hendrik Maes, Willem Hoekstra, Daniel Wilhelmus Elisabeth Verbugt, Daniel Hendrik Jan Maria Hermes