Abstract: Aspects of the present disclosure relate to a photon counting detector and to a read-out integrated circuit to be used in such detector. Aspects of the present disclosure particularly relate to X-ray applications. According to an aspect of the present disclosure, the detector comprises an electrical ground plane arranged at or near an interface between the carrier and at least one ROIC die. Each ROIC die comprises an extension region that laterally extends beyond the photon conversion assembly, wherein peripheral circuitry for a given ROIC die is arranged in the extension region of that ROIC die. The detector comprises at least one electrical connection that connects the power supply line that is arranged on the carrier to the peripheral circuitry of the at least one ROIC die.

Abstract: Aspects of the present disclosure relate to a photon counting detector and to a read-out integrated circuit to be used in such detector. Aspects of the present disclosure particularly relate to X-ray applications. According to an aspect of the present disclosure, the detector comprises an electrical ground plane arranged at or near an interface between the carrier and at least one ROIC die. Each ROIC die comprises an extension region that laterally extends beyond the photon conversion assembly, wherein peripheral circuitry for a given ROIC die is arranged in the extension region of that ROIC die. The detector comprises at least one electrical connection that connects the power supply line that is arranged on the carrier to the peripheral circuitry of the at least one ROIC die.

Abstract: Aspects of the present disclosure relate to an energy-resolving photon counting detector pixel. Further aspects of the present disclosure relate to an energy-resolving photon counting detector comprising a plurality of such pixels, and to an energy-resolving photon counting system comprising the same. In accordance with an aspect of the present disclosure, a CSA base level shift detector is used for determining a shift in the CSA base level over time relative to a first level. The pixel is configured to reset the CSA in dependence of the determined CSA base level shift.

Abstract: Aspects of the present disclosure relate to an energy-resolving photon counting detector pixel. Further aspects of the present disclosure relate to an energy-resolving photon counting detector comprising a plurality of such pixels. In an embodiment of the present disclosure, the detector pixel is operable in a calibration mode, in which mode an offset unit determines a correction signal to be provided to the detecting unit and/or to the comparing unit for correcting an offset in the detecting unit and/or comparing unit.

Abstract: An apparatus includes a sense module configured to be coupled to at least one power supply, where the sense module has a first leg. The apparatus also includes a replica module having a second leg, where the first and second legs have a common structure. The apparatus further includes a feedback loop configured to cause an output voltage across terminals of the replica module to at least substantially equal an input voltage across terminals of the sense module based on sense currents in the first and second legs. At least one cascode stage coupled to the sense module can be configured to reduce a voltage at which one or more signals from the sense module are referenced. One or more trim units can be used to reduce a gain error and/or an offset error between the input voltage and the output voltage.

Abstract: An apparatus includes a sense module configured to be coupled to at least one power supply, where the sense module has a first leg. The apparatus also includes a replica module having a second leg, where the first and second legs have a common structure. The apparatus further includes a feedback loop configured to cause an output voltage across terminals of the replica module to at least substantially equal an input voltage across terminals of the sense module based on sense currents in the first and second legs. At least one cascode stage coupled to the sense module can be configured to reduce a voltage at which one or more signals from the sense module are referenced. One or more trim units can be used to reduce a gain error and/or an offset error between the input voltage and the output voltage.

Abstract: A circuit includes an input stage configured to receive and amplify an input signal to produce an amplified signal, where the input signal is referenced to a higher voltage and is associated with a common mode voltage. The circuit also includes level shifter resistors configured to level shift the amplified signal to produce a shifted signal. The level shifter resistors are configured to provide a voltage drop so that the shifted signal is referenced to a lower voltage. The input stage may include multiple transistors floating in one or more isolated portions of a substrate, where the transistors perform amplification in the input stage. The circuit may also include circuitry configured to control current through the level shifter resistors so that the voltage drop depends on the common mode voltage of the input signal. In addition, the lower voltage may be between supply rails of the circuit.

Abstract: A circuit includes an input stage configured to receive and amplify an input signal to produce an amplified signal, where the input signal is referenced to a higher voltage and is associated with a common mode voltage. The circuit also includes level shifter resistors configured to level shift the amplified signal to produce a shifted signal. The level shifter resistors are configured to provide a voltage drop so that the shifted signal is referenced to a lower voltage. The input stage may include multiple transistors floating in one or more isolated portions of a substrate, where the transistors perform amplification in the input stage. The circuit may also include circuitry configured to control current through the level shifter resistors so that the voltage drop depends on the common mode voltage of the input signal. In addition, the lower voltage may be between supply rails of the circuit.

Abstract: A novel, small outline molded, high voltage, lead frame based integrated circuit package is described. The integrated circuit die has at least one high voltage I/O pad that is electrically connected to an associated high voltage lead/pin in the lead frame. All of the pins of the lead frame that are not high voltage pins have a standard pitch between adjacent pins on the same side of the lead frame that is no more than approximately 0.5 mm. The pitch between each high voltage pin and an adjacent pin is double the standard pitch. The high voltage I/O pad is arranged to handle output signals having voltages of at least 30 volts. In some embodiments, the lead frame is formed from a copper or copper alloy based material and exposed portions of the pins are plated with a lead/tin based solder material.

Abstract: A method and apparatus for handling bad pixels in an image sensor array includes processing data values associated with the pixels of the image sensor. Processing the data values is performed by at least a first pass process and a subsequent pass process. In the first pass, the data values associated with the pixels are analyzed to determine whether any of the pixels are bad pixels. Information identifying the bad pixels is stored in a memory storage area of limited size. The stored information may also include an indicator, indicating a confidence level in categorizing the bad pixel. During the first pass, an overflow mark is stored in the memory storage area when insufficient memory storage is available for storing the information about a particular bad pixel. The overflow mark identifies the particular pixel in the image sensor array.

Abstract: A constant-transconductance rail-to-rail CMOS input circuit with offset trim is provided. PMOS and NMOS differential trim stages are scaled versions of PMOS and NMOS input stages respectively. The differential trim stages are configured to adjust the offset of the differential output current with accuracy over temperature. A first current mirror circuit is configured to receive a fraction of a bias current (?I), where ? is related to the input common mode voltage. A second current mirror circuit is configured to receive another fraction of the bias current ((1??)I). The first current mirror circuit is configured to provide current ?I to the PMOS input stage, and a scaled-down version of current ?I to the PMOS differential trim stage. The second current mirror circuit is configured to provide current ((1??)I) to the NMOS input stage, and a scaled-down version of current ((1??)I) to the differential PMOS trim stage.

Abstract: An automatic exposure system is arranged to dynamically adjust the exposure time and gain of a pixel array in an imaging system. A selected group of pixels from the pixel array are evaluated while the pixel array is exposed to light that is reflected from a scene. The signal levels associated with the selected pixels are compared to a dynamically adjusted exposure threshold level, while the current exposure time is compared to a dynamic adjusted exposure time limit. The exposure threshold level and exposure time limit are selected using a method that is optimized for lower noise and less blur in the resulting image. The optimization method includes an optimal exposure method, an extrapolative method, an iterative method, and an alternative iterative method. The optimization methods are arranged to find an optimum balance between exposure time and gain such that noise and motion blur are minimized in the resulting image.

Abstract: An automatic exposure system is arranged to dynamically adjust the exposure time of a pixel array in an imaging system. A selected group of pixels from the pixel array are evaluated using a non-destructive readout procedure to determine the proper exposure time for the pixel array, while the pixel array is exposed to light that is reflected from a scene. Threshold detectors are employed to compare the signals from the selected group of pixels to a peak level that corresponds to a threshold limit for the pixels. The exposure of the pixel array is terminated when at least one pixel from the selected group of pixels exceeds the threshold limit. The threshold limit may be set to a level that is below total saturation for the pixels such that an overexposure margin is provided. Enhanced image contrast is achieved using automatic exposure time adjustment.

Abstract: A differential voltage amplifier includes a dynamic level shifter circuit and an amplifier circuit. The dynamic level shifter circuit includes high-impedance current sources and resistors that are arranged to move the common-mode levels of a differential input signal to a signal level that is suitable for the amplifier circuit. The amplifier circuit may be single-ended or differential. The dynamic level shifter circuit may include one or more current sources that are arranged to provide improved performance for low common-mode levels. A dynamic biasing scheme may be employed to improve operation over varied common-mode ranges. A trimming circuit may be used to adjust offsets in the system. A DC chop arrangement may be employed to remove offsets in the system.

Abstract: An improved vertical photo-detector cell is used in an imaging sensor. Sensor material associated with a given color in a vertical photo-detector cell is coupled to sensor material associated with the same color in an adjacent photo-detector cell such that photo-carriers from adjacent cells are combined. The coupled sensor materials result in an increased size sensor area for the given color. The increased sensor area associated with each pixel in the sensor results in increased sensitivity and improved fill factor for each color. In an imaging sensor array, the vertical photo-detector cells are arranged such that each color plane is arranged in a pattern. Each sensor in a pattern has a central portion and an extending portion. The central portion and the extending portion are each located about a geometrical center that is associated with a pixel in the array.

Abstract: An improved vertical photo-detector cell is used in an imaging sensor. Sensor material associated with a given color in a vertical photo-detector cell is coupled to sensor material associated with the same color in an adjacent photo-detector cell such that photo-carriers from adjacent cells are combined. The coupled sensor materials result in an increased size sensor area for the given color. The increased sensor area associated with each pixel in the sensor results in increased sensitivity and improved fill factor for each color. In an imaging sensor array, the vertical photo-detector cells are arranged such that each color plane is arranged in a pattern. Each sensor in a pattern has a central portion and an extending portion. The central portion and the extending portion are each located about a geometrical center that is associated with a pixel in the array.

Abstract: The present invention is directed to a photogate based pixel cell with an electronic shutter and which provides relatively low lag and high sensitivity for sensing infrared light reflected from objects. Additionally, this invention eliminates the need for a transfer gate in the pixel cell. In one embodiment, the reset and shutter transistors are implemented with PMOS transistors so that the pixel cell can have an increased dynamic range and a relatively high voltage swing. In another embodiment, the actual size of each pixel cell can be further reduced when the reset gate and the electronic shutter are implemented with NMOS transistors. Also, when a P− well is not disposed beneath the photogate, the ability of the pixel cell to sense infrared light is improved. Correlated double sampling can be used to improve the accuracy of the signal read out from the pixel cell.

Abstract: An image sensing pixel cell includes a reset circuit, a capacitance, a photodiode, an amplifier circuit, and a voltage buffer. The reset circuit couples an initial voltage to a first node at an initial time, where the capacitance stores the initial voltage. The amplifier circuit is arranged to bias the photodiode at a relatively constant voltage. The voltage buffer circuit buffers the first node to produce a second voltage that corresponds to the voltage at the first node at a subsequent time. The second voltage is different from the initial voltage when a photocurrent flows in the photodiode. A pixel cell may include a shutter circuit having a closed position and an open position. The shutter circuit provides a conductive path for the photocurrent between the photodiode and a power supply connection when in the closed position. The shutter circuit provides another conductive path for the photocurrent between the photodiode and the first node when in the open position.

Abstract: A method and apparatus are provided for adjusting an offset in an electronic circuit by shifting at least one threshold voltage of a MOS transistor in an electronic circuit. By biasing a transistor into hard saturation, with sufficient supply voltage, charge carriers will be injected into the oxide layer of the MOS transistor over a predetermined time interval. Injection of charge carriers into the oxide layer of a MOS transistor causes the absolute value of the MOS transistor threshold voltage to increase. The injection of charge carriers is used to either intentionally increase or decrease the offset voltage in an electronic circuit due to mismatched components, process variations or to improve overall system accuracy or performance. In an operational amplifier or comparator, systematic offset voltage is measured at the output of the amplifier, and the threshold voltages of the differential input stage transistors are adjusted accordingly.

Abstract: An active pixel sensor cell array including a XDR reset signal generation circuit configured to generate XDR reset signals having user-selected levels, and an XDR reset signal generation circuit for use with such an array. The XDR reset signal generation circuit includes a digital-to-analog converter (DAC) coupled to receive control bits which determine the level and time of assertion of each XDR reset signal, and a level shifting circuit coupled to the output of the DAC. In response to the control bits (typically a sequence of multi-bit words), the circuit asserts a time-varying XDR reset potential. The XDR reset potential's amplitude as function of time (during each integration period) determines the breakpoints of each cell's response curve.