Patents by Inventor Willem L. Repko

Willem L. Repko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7738501
    Abstract: A method is disclosed for recovering timing information between master and slave nodes interconnected over a packet network having an underlying time grid with a distinct granularity. A series timing packets are exchanged between said master and slave nodes to measure the time offset of the time grid relative to clocks at the master and slave clocks. This offset is then used to either adjust the local clock at the slave node, or generate the clock using a digital controlled oscillator.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: June 15, 2010
    Assignee: Zarlink Semiconductor, Inc.
    Inventors: Willem L. Repko, Robertus Laurentius Van der Valk
  • Patent number: 7385990
    Abstract: A method of recovering timing information in a packet network is disclosed wherein a modulation scheme is used to transport additional information required for clock recovery between the sender and receiver across the network.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: June 10, 2008
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Willem L. Repko, Robertus L. Van Der Valk, Petrus W. Simons, Steven Roos
  • Patent number: 7376156
    Abstract: Disclosed is a method of aligning clocks over multiple networks having different clock domains. The method comprises transmitting timestamped packets over said networks between source and destination nodes, said timestamped packets conveying timing information based on a source clock at said source node, determining the expected delay over multiple nodes for a given traffic density, identifying at least one intermediate node between said source and destination node where said determined expected delay is such as to permit clock restoration within predefined acceptable parameters, restoring said source clock at said at least one intermediate restoration node to generate a restored intermediate clock signal, producing from said restored intermediate clock signal new timestamped packets conveying timing information based on said restored intermediate clock signal, and forwarding said new timestamped packets to said destination node.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: May 20, 2008
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Willem L. Repko, Robertus Laurentius Van Der Valk, Petrus W. Simons
  • Patent number: 7356036
    Abstract: Disclosed is a method of distributing a number of reference clocks across a packet network. The packet network has a master node and one or more slave nodes, the master node and each slave node having basis clocks. A sender sends time-stamped synchronization packets to said one or more slave nodes, and a receiver at the slave nodes receives the time-stamped synchronization packets and synchronizes the basis clocks in the slave nodes with the basis clock in the master node. Multiple reference clocks are encoded with respect to the basis clock in the master node to generate numerical information describing the reference clock(s) in relation to the basis clock in the master node. The basis clock in each of the slave node is synchronized to the basis clock in the master node using time-stamped synchronization packets. The one or more reference clocks are recovered at the slave nodes using said numerical information describing the reference clock(s) in relation to the basis clock in the master node.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: April 8, 2008
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Robertus Laurentius Van Der Valk, Willem L. Repko
  • Patent number: 7315546
    Abstract: Disclosed is a method and apparatus for aligning clock domains over an asynchronous network between a source controlled by a first clock and a destination controlled by a second clock. The predicted delay is estimated for transmitting packets between a source and destination over the network. The time-stamped synchronization packets are sent to the destination, each time-stamped synchronization packet carries timing information based on a master clock at the source. A set of synchronization packets are received at the destination to create a set of data points, and the set of data points is weighted so that synchronization packets exhibiting a delay further from the expected delay are accorded less weight than synchronization packets exhibiting a delay closer to the expected delay. The expected delay is updated to create a current delay estimate based on the set of data points taking into account the different weighting of the data points.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: January 1, 2008
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Willem L. Repko, Robertus L. Van Der Valk, Petrus W. Simons, Craig Barrack
  • Publication number: 20040264477
    Abstract: Disclosed is a method and apparatus for aligning clock domains over an asynchronous network between a source controlled by a first clock and a destination controlled by a second clock. The predicted delay is estimated for transmitting packets between a source and destination over the network. The time-stamped synchronization packets are sent to the destination, each time-stamped synchronization packet carries timing information based on a master clock at the source. A set of synchronization packets are received at the destination to create a set of data points, and the set of data points is weighted so that synchronization packets exhibiting a delay further from the expected delay are accorded less weight than synchronization packets exhibiting a delay closer to the expected delay. The expected delay is updated to create a current delay estimate based on the set of data points taking into account the different weighting of the data points.
    Type: Application
    Filed: February 18, 2004
    Publication date: December 30, 2004
    Applicant: Zarlink Semiconductor Inc.
    Inventors: Willem L. Repko, Robertus L. Van Der Valk, Petrus W. Simons, Craig Barrack
  • Publication number: 20040264478
    Abstract: Disclosed is a method of distributing a number of reference clocks across a packet network. The packet network has a master node and one or more slave nodes, the master node and each slave node having basis clocks. A sender sends time-stamped synchronization packets to said one or more slave nodes, and a receiver at the slave nodes receives the time-stamped synchronization packets and synchronizes the basis clocks in the slave nodes with the basis clock in the master node. Multiple reference clocks are encoded with respect to the basis clock in the master node to generate numerical information describing the reference clock(s) in relation to the basis clock in the master node. The basis clock in each of the slave node is synchronized to the basis clock in the master node using time-stamped synchronization packets. The one or more reference clocks are recovered at the slave nodes using said numerical information describing the reference clock(s) in relation to the basis clock in the master node.
    Type: Application
    Filed: February 18, 2004
    Publication date: December 30, 2004
    Applicant: Zarlink Semiconductor Inc.
    Inventors: Robertus Laurentius Van Der Valk, Willem L. Repko
  • Publication number: 20040223518
    Abstract: Disclosed is a method of aligning clocks over multiple networks having different clock domains. The method comprises transmitting timestamped packets over said networks between source and destination nodes, said timestamped packets conveying timing information based on a source clock at said source node, determining the expected delay over multiple nodes for a given traffic density, identifying at least one intermediate node between said source and destination node where said determined expected delay is such as to permit clock restoration within predefined acceptable parameters, restoring said source clock at said at least one intermediate restoration node to generate a restored intermediate clock signal, producing from said restored intermediate clock signal new timestamped packets conveying timing information based on said restored intermediate clock signal, and forwarding said new timestamped packets to said destination node.
    Type: Application
    Filed: February 18, 2004
    Publication date: November 11, 2004
    Applicant: ZARLINK SEMICONDUCTOR INC.
    Inventors: Willem L. Repko, Robertus Laurentius Van Der Valk, Petrus W. Simons
  • Patent number: 5432724
    Abstract: A data processing system for processing parallel first and second sequences of successive first and successive second data, respectively, includes a memory, having a memory input to receive the first and second data for storage; and an operating circuit coupled to a memory output of the memory to receive a predetermined number of selected ones of the stored first data or the predetermined number of selected ones of the stored second data supplied by the memory, and for operating thereon. The memory is operative to store the first and second data provided in parallel at the memory input as first and second fields of a single word, each word being retrievable upon a single access. The system includes a rearrangement circuit, connected between the memory output and the operating circuit for receiving particular words and for alternately and in parallel providing the predetermined number of successive first data and the predetermined number of successive second data to the operating circuit.
    Type: Grant
    Filed: December 2, 1993
    Date of Patent: July 11, 1995
    Assignee: U.S. Philips Corporation
    Inventor: Willem L. Repko