Abstract: A flip-flop is provided having a data gate circuit for receiving input data and generating therefrom first and second complementary internal data signals representative of the input data. A master circuit is coupled to the data gate circuit for receiving a clock pulse and for latching the internal data signals during a predetermined portion of the clock pulse. A slave circuit is coupled to the master circuit for storing the internal data signals. A reset circuit supplies a synchronous reset signal to the master circuit for resetting the first and second complementary internal data signals on the occurrence of the next clock pulse.

Abstract: A master slave flip-flop includes a data gate for receiving the input data and generating therefrom first and second internal data signals, and a master section for latching the internal data signals and for transmitting such signals to a slave section during predetermined portions of a clock signal. In order to render the internal data signals symmetrical with respect to each other and therefore substantially reduce the possibility of transmitting incorrect data to the slave as a result of a race condition in the master section, a Schottky diode is coupled within the data gate to complete a discharge path for one of the internal data lines and thus prevent it from exceeding a predetermined voltage.

Abstract: A transistor-transistor logic circuit includes an output stage comprising a pull-up and pull-down transistor and an input stage for receiving one or more binary logic signals. First and second current drive transistors regulate base drive to the pull-up and pull-down transistors respectively. A first switching transistor turns said first current drive transistor off when the binary signals reach a first logic level. A second switching transistor turns the second current drive transistor on when the binary logic signals reach the first logic level. In this manner, negative reflections at the output of the circuit will not result in the pull-up transistor and its associated current drive transistor being turned off.

Abstract: A transistor-transistor-logic circuit includes a discharge circuit coupled between the base of an output transistor and a reference potential. The discharge circuit includes a transistor whose base and collector terminals are resistively coupled to the base of the output transistor and whose collector terminal is resistively coupled to a reference potential. The emitter of the transistor is also coupled to the reference potential. The transistor in the discharge circuit appears as a finite impedance when the output transistor is on and provides a path for discharging the base-emitter charge storage while the output transistor is turned off. The resistor coupled between the collector of the bypass transistor and the reference potential provides a large but finite impedance path for leakage current in said output transistor. This prevents the output transistor from being turned on by the leakage current.