Abstract: A post-fusing apparatus is provided in an electrostatographic reproduction machine for adding a controlled amount of moisture to a side of a fused toner image carrying copy sheet to control curl. The sheet conditioning apparatus includes a moisturizing agent supply and splitting assembly, including a supply source containing moisturizing agent and a plurality of rotatable metering rollers forming at least first and second moisture splitting nips, for splitting a layer of supplied moisturizing agent, and forming a thin film of moisture. The sheet conditioning apparatus also includes a rotatable moisture applying roller forming a moisture splitting and receiving nip with the moisture agent supply and splitting assembly, for receiving the thin film of moisture therefrom.

Abstract: A paper conditioner to control image dependent curl which uses one or more counter-rotating transfer rollers which are initially spaced from their respective back-up rollers in the intercopy gap, and which come together as the lead edge enters the nip area, and separates when the trail edge is about to pass. This permits the rollers to have a less demanding runout tolerance by bringing the rollers together when the sheet is in the nip, and then articulating the rollers apart in the intercopy gap.

Abstract: A vacuum corrugation feeder employs a vacuum feedhead working in conjunction with an air knife to feed sheets from the top or bottom of a stack. A retractable corrugator is included in the vacuum feedhead which prevents smearing of coated sheets due to relative motion between sheet surfaces and the corrugator.

Abstract: A fault-tolerant storage device array using a copyback cache storage unit for temporary storage. When a Write occurs to the RAID system, the data is immediately written to the first available location in the copyback cache storage unit. Upon completion of the Write to the copyback cache storage unit, the host CPU is immediately informed that the Write was successful. Thereafter, further storage unit accesses by the CPU can continue without waiting for an error-correction block update for the data just written. In a first embodiment of the invention, Read-Modify-Write operations are performed during idle time. In a second embodiment of the invention, normal Read-Modify-Write operation by the RAID system controller continue use Write data in the controller's buffer memory. In a third embodiment, at least two controllers, each associated with one copyback cache storage unit, copy Write data from controller buffers to the associated copyback cache storage unit.

Abstract: A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device Lo the output terminal.

Abstract: A top vacuum corrugation feeder includes articulating suction fingers to assist in raising the top sheet of a stack of sheets to the feedhead of the vacuum corrugation feeder. The suction fingers are rotated down from their interleaved position between feed belts to contact the top sheet in the sheet stack and raises the top sheet to the feed belts. As a result, the feeder can handle heavy sheets, curled sheets, and sheets which are edge welded.

Abstract: A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO.

Abstract: Large numbers of relatively small (e.g., 1.8" or smaller) off-the-shelf disk drives are controlled to maximize the highest throughput performance at the least cost between a host computer and a mass storage subsystem. Host data is stored redundantly so as to form a cache. The controller recognizes data contained in its associated disk cache so as to produce that data to a requesting host with minimum delay. Data not in the disk cache as well as write commands are transferred to the controller of a mass storage subsystem with no substantial delay.

Abstract: Data in a system having dynamic random access memories (DRAM's) is preserved despite loss of the primary source of electrical power to that system. A Flash RAM and a small auxiliary power source are employed by a controller independent of the system to transfer the DRAM contents to the Flash RAM immediately upon loss of primary system power. The data is also automatically returned to the DRAM after return of primary power with special data signals or sequences being utilized in a multiple controller environment so as to award the complete data recovery function to the first controller to demand attention.

Abstract: A RAID-compatible data storage system which allows incremental increases in storage capacity at a cost that is proportional to the increase in capacity. The system does not require changes to the host system. The control and interface functions previously performed by a single (or redundant) central data storage device controller are distributed among a number of modular control units (MCUs). Each MCU is preferably physically coupled to a data storage device to form a basic, low-cost integrated storage node. One of two bus ports interfaces an MCU with the host computer on a host bus, and the other bus port interfaces an MCU with one or more data storage devices coupled to the MCU by a data storage device bus. The serial interface ports provide a means by which each of the MCUs may communicate with each other MCU to facilitate the implementation of a memory array architecture.

Abstract: A RAID-compatible data storage system which allows incremental increases in storage capacity at a cost that is proportional to the increase in capacity. The system does not require changes to the host system. The control and interface functions previously performed by a single (or redundant) central data storage device controller are distributed among a number of modular control units (MCUs). Each MCU is preferably physically coupled to a data storage device to form a basic, low-cost integrated storage node. One of two bus ports interfaces an MCU with the host computer on a host bus, and the other bus port interfaces an MCU with one or more data storage devices coupled to the MCU by a data storage device bus. The serial interface ports provide a means by which each of the MCUs may communicate with each other MCU to facilitate the implementation of a memory array architecture.

Abstract: A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO.

Abstract: A sheet stacking and registration system particularly suited for high speed sequentially stacking of the flimsy printed sheets output of a high speed reproduction apparatus in a sheet stacking area, with a stacking registration position; with a vacuum belt sheet transport system acquiring only a limited lead edge area of the sheets and transporting them over the stacking area with non-slip sheet feeding towards the registration position; and an integral system peeling the lead edges of the sheets off of the vacuum transport and guiding them downwardly and towards the lead edge registration position while reducing but partially maintaining the sheet's vacuum acquisition, and applying a normal force, preferably with a roller pressing down the lead edges of the peeled off sheet against the previously stacked sheets adjacent the registration position, to frictionally slow the sheet as it approaches the registration position, and also holding down the sheet after it reaches the stacking position.

Abstract: A photoreceptor apparatus constructed of a photoreceptor belt releasably attached to the surface of a cylindrical mandrel. The photoreceptor belt is preferably attached to the mandrel by means of a movable segment of the mandrel that is retracted into the mandrel to allow installation of the belt by reducing the effective circumference of the mandrel.

Abstract: A computer storage system having a dual port buffer memory for improved performance. The invention comprises a computer storage subsystem that includes a dual port buffer memory that effectively provides two internal data busses for the storage subsystem: one bus for data transfers between the dual port buffer memory and the storage units, and a second bus for data transfers between the dual port buffer memory and a CPU. The throughput of the storage subsystem is roughly equivalent to the bandwidth of the slower of the two busses. In alternative configurations, the invention may use a plurality of dual port buffer memories in parallel to increase the effective throughput of the storage subsystem, and better match the bandwidth of the two busses.

Abstract: A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device to the output terminal.

Abstract: A fault-tolerant storage device array using a copyback cache storage unit for temporary storage. When a Write occurs to the RAID system, the data is immediately written to the first available location in the copyback cache storage unit. Upon completion of the Write to the copyback cache storage unit, the host CPU is immediately informed that the Write was successful. Thereafter, further storage unit accesses by the CPU can continue without waiting for an error-correction block update for the data just written. In a first embodiment of the invention, Read-Modify-Write operations are performed during idle time. In a second embodiment of the invention, normal Read-Modify-Write operation by the RAID system controller continue use Write data in the controller's buffer memory. In a third embodiment, at least two controllers, each associated with one copyback cache storage unit, copy Write data from controller buffers to the associated copyback cache storage unit.

Abstract: A method for on-line restoration of redundancy information in a redundant array storage system. The invention provides alternative methods of restoring valid data to a storage unit after a Write failure caused by a temporary storage unit fault. In the first preferred method, a valid redundancy block is generated for the corresponding data blocks on all storage units. Resubmitting the interrupted Write operation causes the old (and potentially corrupted) data block to be "subtracted" out of the re-computed redundancy block. The uncorrupted new data block is written over the old data block, and is "added" into the re-computed redundancy block to create a new, corrected redundancy block. The new, corrected redundancy block is written to the appropriate storage unit. In the second preferred method, a new redundancy block is generated from all valid data blocks and the new data block. The new redundancy block and the new data block are then written to the appropriate storage units.

Abstract: An array controller including a DATA-RAM and a SHADOW-RAM. Both the DATA-RAM and the SHADOW-RAM are coupled to a first and second memory interface. Each memory interface has the ability to independently communicate the contents of the SHADOW-RAM over a controller-controller data link to at least one other similar array controller. The memory interface also interfaces the DATA-RAM and the SHADOW-RAM to a CPU, the data storage units of the RAID system, and the controller processor. Write data received from the CPU is stored in the two independent memories in order to ensure that pending Write data (i.e., Write data that has not yet been written to the RAID system, including any copyback cache device) will not be lost. In addition, the two memory interfaces provide redundant access routes which allow Write data to be retrieved by another array controller if the controller processor fails.

Abstract: A fault-tolerant storage device array using a copyback cache storage unit for temporary storage. When a Write occurs to the RAID system, the data is immediately written to the first available location in the copyback cache storage unit. Upon completion of the Write to the copyback cache storage unit, the host CPU is immediately informed that the Write was successful. Thereafter, further storage unit accesses by the CPU can continue without waiting for an error-correction block update for the data just written. In a first embodiment of the invention, Read-Modify-Write operations are performed during idle time. In a second embodiment of the invention, normal Read-Modify-Write operation by the RAID system controller continue use Write data in the controller's buffer memory. In a third embodiment, at least two controllers, each associated with one copyback cache storage unit, copy Write data from controller buffers to the associated copyback cache storage unit.