Abstract: A modulo mi adder and a modulo mi,j scaling unit for use with an RNS. The adder includes a modulo mi barrel shifter, and a dynamic storage unit coupled to the barrel shifter to store the output of the barrel shifter. In a preferred embodiment, the dynamic storage unit includes one dynamic latch for each output line of the barrel shifter, with each of the dynamic latches including a clocked inverter in cascade with an inverter. One modulo mi,j scaling unit includes a modified modulo mi barrel shifter that performs both residue conversion and an arithmetic operation. The residue conversion is performed without using combinational logic. In one preferred embodiment, the modified barrel shifter performs the residue conversion though mi–mj additional columns that replicate normal columns for all modulo mi input lines that are congruent modulo mj.

Abstract: A self-timed data processing circuit module is provided. Data is provided to the data processing circuit along with a Req handshaking input. The data processing circuit has an isochronous processing delay for all data inputs. An example of a data processing circuit with isochronous processing delay is a One Hot Residue Number System arithmetic processing circuit. The data processing circuit processes the input data while the Req input propagates through a delay circuit that has substantially the same processing delay as the data processing circuit. Thus, the propagation delay of the Req signal is substantially equal to the data processing circuit's processing time. This allows the output of the delay circuit to be used to both latch the output of the data processing circuit and provide a “data ready” output.

Abstract: A modulo mi adder and a modulo mi,j scaling unit for use with an RNS. The adder includes a modulo mi barrel shifter, and a dynamic storage unit coupled to the barrel shifter to store the output of the barrel shifter. In a preferred embodiment, the dynamic storage unit includes one dynamic latch for each output line of the barrel shifter, with each of the dynamic latches including a clocked inverter in cascade with an inverter. One modulo mi,j scaling unit includes a modified modulo mi barrel shifter that performs both residue conversion and an arithmetic operation. The residue conversion is performed without using combinational logic. In one preferred embodiment, the modified barrel shifter performs the residue conversion though mi-mj additional columns that replicate normal columns for all modulo mi input lines that are congruent modulo mj.

Abstract: An arithmetic circuit for use with an RNS is provided. The arithmetic circuit includes an arithmetic core, test circuitry, and logic circuitry. The arithmetic core performs an RNS arithmetic operation, and the test circuitry verifies proper circuit delay by inducing oscillation at the output of the arithmetic core during testing. The logic circuitry produces a pass/fail signal based on whether the oscillation frequency of the arithmetic core is at least equal to a minimum threshold value. In one preferred embodiment, the logic circuitry includes a counter that counts oscillations of the output of the arithmetic core during testing, and a comparator that compares the output of the counter after a predetermined test period with the minimum threshold value. Also provided is a method for testing the propagation delay of an RNS arithmetic circuit having an arithmetic core.

Abstract: A self-timed data processing circuit module is provided. Data is provided to the data processing circuit along with a Req handshaking input. The data processing circuit has an isochronous processing delay for all data inputs. An example of a data processing circuit with isochronous processing delay is a One Hot Residue Number System arithmetic processing circuit. The data processing circuit processes the input data while the Req input propagates through a delay circuit that has substantially the same processing delay as the data processing circuit. Thus, the propagation delay of the Req signal is substantially equal to the data processing circuit's processing time. This allows the output of the delay circuit to be used to both latch the output of the data processing circuit and provide a “data ready” output.

Abstract: A direct digital frequency synthesizer employs residue number system based processors to generate output waveforms of desired frequencies. The frequency synthesizer includes a phase accumulator comprising a plurality of individual adders, each adding a predefined quantity to a digit of a frequency setting word in which the individual digits are residue digits of differing moduli. The outputs of the independent adders form a combined residue output word which is used to address a memory storing signal samples. In one embodiment of the invention, the memory is a dual port ROM storing samples of one-quarter of a sine wave and the dual port ROM is simultaneously addressed to read a selected sample and an associated sample corresponding to the magnitude of a sample of the sine wave advanced by 90.degree. from the first sample.