Abstract: A system of and method for extended Booth encoding of two binary numbers, K and L. A stage of the encoder receives K[2n+1], K[2n], L[2n+1], and C[n−1], N−1≧n≧0, with N being the length of L, and it being assumed L[2n]=0, and forms C[n], S[n], M1[n], and M2[n] according to the following equations: C[n]=K[2n+1]|L[2n+1], S[n]=K[2n+1]{circumflex over ( )}L[2n+1], M1[n]=K[2n]{circumflex over ( )}C[n−1], M2[n]=(S[n]&/K[2n]&/C[n−1])|(/S[n]&K[2n]&C[n−1]), where | refers to the logical OR function, {circumflex over ( )} to the exclusive OR function, & to the logical AND function, and/to the logical inversion function.

Abstract: An equalizer for equalizing channel multi-path distortion includes digital filters. To improve the convergence speed and tracking ability of the equalizer while lowering noise and power consumption, the digital filters are divided into sections. Various parameters of the sections, such as step-size, shutdown and update rates can be controlled. Control of the various parameters can be realized either in software on an embedded or external processor or by dedicated hardware.

Abstract: An information display system is provided having a transmitter and a plurality of uniquely identified display terminals, each terminal having an IR receiver. Uniquely identified sets of messages are transmitted in by the IR transceiver for reception by the display terminals. Between each set of transmissions, the receiver is periodically activated. Once the presence of a transmission is sensed by the receiver, a timer forces the receiver to remain activated while it compares the uniquely identified received messages to the display terminals unique identification. The receiver stores the message that matches the identification of the display terminal and the timer forces the receiver to remain deactivated at least until the entire set of transmissions has been completed.

Abstract: The present invention comprises an electrical test circuit for testing a signal in a digital circuit, to detect common analog signal deficiencies or "faults". More specifically, the test circuit can simultaneously detect one or all of three such faults in a digital circuit, including: (1) a voltage spike which occurs when the signal briefly jumps either high or low; (2) a float fault which occurs when the signal is floating for too long; and (3) a noise fault which occurs when the signal passes from either the high or the low state to the float state, and then returns directly to the same state. The signal to be tested is first processed in an input state discriminator to classify it by state, either high, low, or float. In a preferred embodiment, both the high voltage threshold and the low voltage threshold of the input state discriminator are adjustable separately to accommodate all logic families.

Abstract: Clock signals, data words and qualifier signals are received via monitor probes during a data acquisition mode, selected data words being stored in a memory in response to the clock and qualifier signals. The stored data words may then be displayed in a tabular or a map format on a cathode ray tube screen. Data words may be acquired randomly, i.e., in a free-running sampling mode, or acquired selectively by using pattern recognition and delay trigger circuits. Using the tabular display format, data words are displayed as ones and zeroes. Using the map display format, each data word thus acquired is displayed on the CRT screen as a dot during a subsequent display mode. The position of each dot on the CRT screen uniquely identifies its address or state value. The most significant bits determine the vertical position on the CRT screen and the least significant bits determine the horizontal position of the dot. The intensity of the dot indicates the relative frequency of occurrence of that logic state.

Abstract: A digital pattern triggering circuit combines an addressable memory and a processor. Input data patterns address corresponding memory elements whereby data previously stored in the memory by the processor is accessed, providing an indication of whether a preselected data pattern has occurred.

Abstract: Clock signals, data words and qualifier signals are received via monitor probes during a data acquisition mode, selected data words being stored in a memory in response to the clock and qualifier signals. The stored data words may then be displayed in a tabular or a map format on a cathode ray tube screen. Data words may be acquired randomly, i.e., in a free-running sampling mode, or acquired selectively by using pattern recognition and delay trigger circuits. Using the tabular display format, data words are displayed as ones and zeroes. Using the map display format, each data word thus acquired is displayed on the CRT screen as a dot during a subsequent display mode. The position of each dot on the CRT screen uniquely identifies its address or state value. The most significant bits determine the vertical position on the CRT screen and the least significant bits determine the horizontal position of the dot. The intensity of the dot indicates the relative frequency of occurrence of that logic state.

Abstract: Data flow between multiple digital circuits having various internal clock rates is controlled by an asynchronous trigger bus. A trigger pulse is generated on the trigger bus when a trigger condition is simultaneously detected in two circuits desiring to communicate.