Abstract: A segmented subsystem, for use within an automated test platform, includes a first subsystem segment including a first data sequencer configured to coordinate the execution of one or more instructions within the first subsystem segment. A second subsystem segment includes a second data sequencer configured to coordinate the execution of one or more instructions within the second subsystem segment.

Abstract: A scalable test platform includes a PCIe-based event fabric. One or more CPU subsystems are coupled to the PCIe-based event fabric and configured to execute an automated test process. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test.

Abstract: A scalable test platform includes a PCIe-based event fabric. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test and generate captured test data. One or more digital signal processing subsystems are coupled to the PCIe-based event fabric and configured to process the captured test data.

Abstract: A method, computer program product, and computing system for, upon the occurrence of a computer-related event, comparing code utilized by one or more subsystems included within a scalable test platform to code available from a remote location. If the code available from the remote location is newer than the code utilized by one or more subsystems, the code available from the remote location is obtained, thus defining newer code. The code utilized by one or more subsystems is updated with the newer code.

Abstract: A segmented subsystem, for use within an automated test platform, includes a first subsystem segment configured to execute one or more instructions within the first subsystem segment. A second subsystem segment is configured to execute one or more instructions within the second subsystem segment. The first subsystem segment includes: a first functionality, a second functionality, and a status polling engine. The status polling engine is configured to: determine a first status for the first functionality and a second status for the second functionality, and generate a consolidated status indicator for the first subsystem segment based, at least in part, upon the first status for the first functionality and the second status for the second functionality.

Abstract: A scalable test platform includes a PCIe-based event fabric. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test and generate captured test data.

Abstract: A method, computer program product, and computing system for, upon the occurrence of a computer-related event, comparing code utilized by one or more subsystems included within a scalable test platform to code available from a remote location. If the code available from the remote location is newer than the code utilized by one or more subsystems, the code available from the remote location is obtained, thus defining newer code. The code utilized by one or more subsystems is updated with the newer code.

Abstract: A segmented subsystem, for use within an automated test platform, includes a first subsystem segment configured to execute one or more instructions within the first subsystem segment. A second subsystem segment is configured to execute one or more instructions within the second subsystem segment. The first subsystem segment includes: a first functionality, a second functionality, and a status polling engine. The status polling engine is configured to: determine a first status for the first functionality and a second status for the second functionality, and generate a consolidated status indicator for the first subsystem segment based, at least in part, upon the first status for the first functionality and the second status for the second functionality.

Abstract: A scalable test platform includes a PCIe-based event fabric. One or more CPU subsystems are coupled to the PCIe-based event fabric and configured to execute an automated test process. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test.

Abstract: An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the hardware layer. The software layer communicates in device under test terms whereas the hardware layer communicates in the terms of the testing apparatus. Various communication interface points are provided to the software and hardware layers, as well as the interface for tester abstraction.

Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.

Abstract: An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the hardware layer. The software layer communicates in device under test terms whereas the hardware layer communicates in the terms of the testing apparatus. Various communication interface points are provided to the software and hardware layers, as well as the interface for tester abstraction.

Abstract: An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the hardware layer. The software layer communicates in device under test terms whereas the hardware layer communicates in the terms of the testing apparatus. Various communication interface points are provided to the software and hardware layers, as well as the interface for tester abstraction.

Abstract: A method for linking compiled pattern data and loading the data into tester hardware includes the steps of generating a composite object that includes a shared resource, determining a local shared resource specific to a test instrument that is associated with the shared resource in the composite object, assigning a local reconciled value or address to the local shared resource, and loading the local shared resource into the test instrument.

Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.

Abstract: Method and apparatus for calibrating timing accuracy during testing of integrated circuits. An ATE type (automatic test equipment) integrated circuit tester calibrates itself to reference blocks (dummy ICs) that have the same relevant dimensions as the integrated circuits to be tested and have fit into the test fixture. The number of reference blocks required is equal to the number of signal terminals on the integrated circuit to be tested subject to timing calibration where typically the number of signal terminals is less than the total number of signal terminals on the IC being tested and is typically a relatively small number, e.g., 9. This is useful in the case of high pin count integrated circuits where the pins are grouped into relatively small numbers of pins which are source synchronous. A signal trace electrically connects a different signal terminal to a common reference terminal on each reference block in the set.

Abstract: A method and apparatus for calibrating tester timing accuracy during testing of integrated circuits. An ATE tester measures itself through reference blocks that have the same relevant dimensions as the integrated circuits to be tested. The number of reference blocks required is equal to the number of signal terminals on an integrated circuit to be tested being subject to timing calibration. A signal trace electrically connects a different signal terminal to a common reference terminal on each reference block. Each signal trace used should be closely matched both physically and electrically to the other signal traces used in the set of reference blocks, so that the electrical path length associated with each trace is nearly identical. To perform the timing calibration, the reference blocks may be mounted on a single fixture one at a time, or using multi-site fixtures, multiple reference blocks may be used in parallel.

Abstract: Method and apparatus for calibrating timing accuracy during testing of integrated circuits. An ATE type (automatic test equipment) integrated circuit tester calibrates itself to reference blocks (dummy ICs) that have the same relevant dimensions as the integrated circuits to be tested and have fit into the test fixture. The number of reference blocks required is equal to the number of signal terminals on the integrated circuit to be tested subject to timing calibration where typically the number of signal terminals is less than the total number of signal terminals on the IC being tested and is typically a relatively small number, e.g., 9. This is useful in the case of high pin count integrated circuits where the pins are grouped into relatively small numbers of pins which are source synchronous. A signal trace electrically connects a different signal terminal to a common reference terminal on each reference block in the set.