Abstract: A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.

Abstract: Basically, this invention provides for an inbred corn line designated G07-NPID2449, methods for producing a corn plant by crossing plants of the inbred line G07-NPID2449 with plants of another corn plants. The invention relates to the various parts of inbred G07-NPID2449 including culturable cells. This invention also relates to methods for introducing transgenic transgenes into inbred corn line G07-NPID2449 and plants produced by said methods.

Abstract: The present invention is directed to a system and method for adding programmer visible features to a microprocessor by using partially-explicit ISA constructs. The system includes a language for expressing the partially-explicit ISA constructs that describe VLIW instruction formats, slots, and operations. These partially-explicit instruction set constructs are used in conjunction with prior art instruction set constructs to describe a complete instruction set. The system also includes a method for converting a partially-explicit instruction set to an explicit instruction set, which can then be used as described in prior art processor generation systems to generate fully-pipelined micro-architectural implementations in the form of synthesizable HDL, and to generate software components for extending software development tools for the microprocessor.

Abstract: A six degree of freedom force reflecting haptic interface includes three powered axes and three free axes, all of which are tracked so that the position of a user connection element in the work volume can be determined. The interface includes cable drives with polymer composite or metallic cables, automatic cable tensioning devices, and grounded actuator capstans. A nested hub and transfer drive provide a compact, weight balanced interface. User comfort and safety features are also provided.

Abstract: Methods and apparatus for switching Fiber Channel Arbitrated Loop Systems is provided between a plurality of Fiber Channel Loop devices. In one aspect of the invention, the system switches based at least in part on arbitrated loop primitives. An exemplary interconnect system may include a first port and a second port, both including port logic to monitor certain arbitrated loop primitives, a connectivity apparatus, a route determination apparatus including a routing table consisting of ALPA addresses and their associated ports, the route determination apparatus coupled to each port and the connectivity apparatus, where the connectivity apparatus creates paths between the ports based on arbitrated loop primitives. In one embodiment, the connectivity apparatus is a crossbar switch. Examples of the arbitrated loop primitives that cause the switch to create paths between ports includes one or more of the following: ARB, OPN and CLS.

Abstract: Methods and apparatus for switching Fibre Channel Arbitrated Loop Systems is provided between a plurality of Fibre Channel Loop devices. In one aspect of the invention, the system switches based at least in part on arbitrated loop primitives. An exemplary interconnect system may include a first port and a second port, both including port logic to monitor certain arbitrated loop primitives, a connectivity apparatus, a route determination apparatus including a routing table consisting of ALPA addresses and their associated ports, the route determination apparatus coupled to each port and the connectivity apparatus, where the connectivity apparatus creates paths between the ports based on arbitrated loop primitives. In one embodiment, the connectivity apparatus is a crossbar switch. Examples of the arbitrated loop primitives that cause the switch to create paths between ports includes one or more of the following: ARB, OPN and CLS.

Abstract: Methods and apparatus for switching Fiber Channel Arbitrated Loop Systems is provided between a plurality of Fiber Channel Loop devices. In one aspect of the invention, the system switches based at least in part on arbitrated loop primitives. An exemplary interconnect system may include a first port and a second port, both including port logic to monitor certain arbitrated loop primitives, a connectivity apparatus, a route determination apparatus including a routing table consisting of ALPA addresses and their associated ports, the route determination apparatus coupled to each port and the connectivity apparatus, where the connectivity apparatus creates paths between the ports based on arbitrated loop primitives. In one embodiment, the connectivity apparatus is a crossbar switch. Examples of the arbitrated loop primitives that cause the switch to create paths between ports includes one or more of the following: ARB, OPN and CLS.

Abstract: Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph.

Abstract: A multi-function force reflecting haptic interface including various sub-assemblies is disclosed. The sub-assemblies include multiple function user interfaces, a user interface docking station for setting the interface to a home position, temperature monitoring and control systems, and various kinematic cable drive systems.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: The present invention relates to a system and method for sampling a gas flow to measure one or more contaminants within a semiconductor processing tool. The system includes a portable unit containing one or more dry traps, Tenax traps and, if desired, wet impingers. The unit is coupled to a gas flow in a clean room and the dry traps. Tenax traps and wet impingers measure contaminants contained in the gas supply for a determined sampling interval. When the sampling interval is done, the unit is sent to an analysis facility for processing.

Abstract: Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations.

Abstract: The invention provides a system and method comprising an apparatus for removing contaminants from a gas in a semiconductor processing device, which can include a filter unit having at least two parallel filter stages located therein. The filter stages are designed to remove a least a portion of the contaminants present in the gas flowing through them. The apparatus can also include a flow controller for distributing the gas flow among the filter stages. In one embodiment, the controller may consist of a diffuser plate. The invention also provides a sampling tube orifice for gas flow control in a system or method of the invention. In another embodiment, an apparatus for removing contaminants from a gas in a clean room comprises a filter unit having at least two parallel filter stages, which are used to remove a portion of the contaminants in the gas as it passes through the apparatus.

Abstract: The present invention provides passive sampling systems and methods for monitoring contaminants in a semiconductor processing system. In one embodiment, that passive sampling system comprises a collection device in fluid communication with a sample line that provides a flow of gas from a semiconductor processing system. The collection device is configured to sample by diffusion one or more contaminants in the flow of gas.

Abstract: Controlling accesses to target devices such as disk drives by modifying the duty cycle profile of those devices to improve device reliability is disclosed. The utilization of a target device is monitored, and if a device is being overused, that device is given a rest period by reserving it for a special initiator that does not send any commands to the device for a certain period of time. This reduced utilization has the effect of increasing the reliability of the target device. This period of time also adds a delay to the processing of commands for the target device being overutilized so that the device becomes less responsive. This performance penalty creates pressure on system administrators to reduce the number of commands sent to that target device and/or move data to proper devices (that can handle the high number of accesses).

Abstract: Auto-discrimination between FC and SATA devices upon insertion of a device into a port of a FAST-compatible switch is disclosed. Without user intervention, the port is able to determine the type of device attached, set the appropriate data rate in the Phy or SERDES and, in the case of FC or SATA drives, start the disk insertion process into the active switch zones. The SERDES is first initialized to FC speeds, and the receive path is searched for a receive signal. Upon detecting a receive signal, the detection circuitry then checks to see if a valid SATA Out Of Band (OOB) sequence is received. If a valid SATA OOB sequence is received, the SERDES is configured for SATA speeds and analog settings. If a valid SATA OOB sequence is not received, and instead a FC auto-negotiation process runs to completion, the SERDES remains at FC speeds.

Abstract: The invention provides systems and methods for using a “haptic camera” within a virtual environment and for using graphical data from the haptic camera to produce touch feedback. The haptic camera obtains graphical data pertaining to virtual objects within the vicinity and along the trajectory of a user-controlled haptic interface device. The graphical data from the camera is interpreted haptically, thereby allowing touch feedback corresponding to the virtual environment to be provided to the user.