Abstract: Electro-absorption modulators (EAM) and monolithically integrated electro-absorption modulated lasers (EML) and methods of fabrication are disclosed. Vertically stacked waveguides for a distributed feedback (DFB) laser, an electro-absorption modulator (EAM) and a passive output waveguide are vertically integrated, and the DFB laser, EAM and output waveguide are optically coupled using laterally tapered vertical optical couplers. Laterally tapered vertical optical couplers provides an alternative to conventional butt-coupling of a laser and EAM, offering improved reliability for high power operation over extended lifetimes. Optionally, the EML comprises monolithically integrated electronic circuitry, e.g., driver and control electronics for the DFB laser and EAM. Beneficially, integrated EAM driver and control circuitry comprises a high-speed electro-optical control loop for very high-speed linearization and temperature compensation, e.g.

Abstract: An optical receiver comprises a monolithically integrated pin photodiode (PIN) and transimpedance amplifier (TIA). The TIA comprises InP heterojunction bipolar transistors (HBT) fabricated from a first plurality of layers of an epitaxial layer stack grown on a SI:InP substrate; the PIN is fabricated from a second plurality of layers of the epitaxial layer stack. The p-contact of the PIN is directly connected to the input of the TIA to reduce PIN capacitance CPIN. The TIA capacitance CTIA may be matched to CPIN. Device parameters comprising: a thickness of the absorption layer, window area, and an optional mirror thickness of the PIN; device capacitance CPIN+CTIA; and feedback resistance RF of the TIA; are optimized to performance specifications comprising a specified sensitivity and responsivity at an operational wavelength. This design approach enables cost-effective fabrication an integrated PIN-TIA, for applications such as a 1577 nm receiver for an ONU for 10G-PON.

Abstract: An electro-absorption modulator (EAM) comprising an integrated high speed electro-optical control loop for very high-speed linearization and temperature compensation for analog optical data center interconnect applications is disclosed. The control loop can function in a stable manner because the electronics and optical components are monolithically integrated on a single substrate in small form factor. Because of the small size enabled by monolithic integration, the temperatures of the optical blocks and electronics blocks are tightly coupled, and the control loop time delays and phase delays are small enough to be stable, even for very high frequency operation. This arrangement enables a low cost, low power analog transmitter implementation for data center optical interconnect applications using advanced modulation schemes, such as PAM-4 and DP-QPSK.

Abstract: An integrated high speed electro-optical control loop for very high-speed linearization and temperature compensation of an electro-absorption modulator (EAM) for analog optical data center interconnect applications is disclosed. The control loop can function in a stable manner because the electronics and optical components are monolithically integrated on a single substrate in small form factor. Because of the small size enabled by monolithic integration, the temperatures of the optical blocks and electronics blocks are tightly coupled, and the control loop time delays and phase delays are small enough to be stable, even for very high frequency operation. This arrangement enables a low cost, low power analog transmitter implementation for data center optical interconnect applications using advanced modulation schemes, such as PAM-4 and DP-QPSK.

Abstract: A logic gate comprises a bipolar switching transistor and a depletion mode field effect load device. A current independent voltage source and a voltage independent current source are connected in series between an input terminal of the logic gate and a base of the bipolar transistor. The voltage independent current source is a depletion mode field effect transistor having a source and drain which are connected in series with the current independent voltage source and the base of the bipolar transistor. A feedback device is connected in series between a gate of the current source field effect transistor and a gate of the load transistor. A discharge device is connected in parallel with the current independent voltage source for actively discharging a base-emitter junction of the bipolar transistor during switching of the bipolar transistor from an on state to an off state. The logic gate is particularly suitable for use in memory elements.