Patents by Inventor William A. Halliday

William A. Halliday has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240107152
    Abstract: An image capture system provides automated prompts for aiding a user in capturing images for use in 3D model creation. While a user is preparing to capture an image, the system provides visual indications that indicate whether a quality-based condition is satisfied. Based on the visual indications, a user can determine whether an image, if captured, would likely be suitable for use in creating a 3D model. Determining if the quality-based condition is satisfied may include monitoring output generated by one or more sensors and comparing the output against a threshold value. Additionally, the system may analyze the visual content or metadata associated with an image to determine if the quality-based condition is satisfied and request user input to further identify certain image features that were identified by the system.
    Type: Application
    Filed: September 29, 2023
    Publication date: March 28, 2024
    Inventors: Manish Upendran, William Castillo, Derek Halliday
  • Publication number: 20230302683
    Abstract: In a method, substrate elements are provided wherein each substrate element has a first side and a second side meeting at a corner point. The substrate elements are picked and then placed on a support device in alignment. A cutting operation is then performed where each of the substrates elements are cut along a cut line having a common first direction which intersects the first and second sides of each of the substrate elements in order to create a third side on each substrate element. The third side of each of the substrate elements meets the first and the second sides at corresponding corner points.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 28, 2023
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Melodie CHAPERON, William HALLIDAY, Jean GAGNIEUX
  • Patent number: 11610879
    Abstract: A handshake mechanism allows die discovery in a stacked die architecture that keeps inputs isolated until the handshake is complete. Power good indications are used as handshake signals between the die. A die keeps inputs isolated from above until a power good indication from the die above indicates presence of the die above. The die keeps inputs isolated from below until the die detects power is good and receives a power good indication from the die and the die below. In an implementation drivers and receivers, apart from configuration bus drivers and receivers are disabled until a fuse distribution done signal indicates that repairs have been completed. Drivers are then enabled and after a delay to ensure signals are driven, receivers are deisolated. A top die in the die stack never sees a power good indication from a die above and therefore keeps inputs from above isolated. That allows the height of the die stack to be unknown at power on.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: March 21, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Russell J. Schreiber, Richard M. Born, Carl D. Dietz, William A. Halliday
  • Patent number: 11264115
    Abstract: An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 1, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Russell Schreiber, Keith A. Kasprak, Vance Threatt, James A. Wingfield, William A. Halliday, Srinivas R. Sathu, Arijit Banerjee
  • Publication number: 20210407617
    Abstract: An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.
    Type: Application
    Filed: September 22, 2020
    Publication date: December 30, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Russell Schreiber, Keith A. Kasprak, Vance Threatt, James A. Wingfield, William A. Halliday, Srinivas R. Sathu, Arijit Banerjee
  • Patent number: 11169266
    Abstract: A method begins with forming a first wiring layer on a substrate, forming a cavity in the substrate, and laminating a bottom side of the substrate so as to cover a bottom side of the cavity. Next, an integrated circuit is placed within the cavity of the substrate, and then a first optically transparent layer is disposed on the top surface of the substrate to cover a top surface of the integrated circuit. The first optically transparent layer has an aperture formed therein exposing at least a portion of the top surface of the integrated circuit. A second wiring layer is disposed on a top surface of the first optically transparent layer in a pattern that does not obstruct light traveling to or from the top surface of the integrated circuit. The integrated circuit is a laser emitting integrated circuit or a reflected light detector.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: November 9, 2021
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: William Halliday
  • Patent number: 10955289
    Abstract: An electronic module includes an ambient light sensor and a proximity sensor. The ambient light sensor includes an ambient light photodetector. The proximity sensor includes an infrared photoemitter, a reference infrared photodetector and another infrared photodetector. The ambient light sensor is arranged in a stack over the proximity sensor with a position that allows infrared photons transmitted by the infrared photoemitter to be received by the reference infrared photodetector.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: March 23, 2021
    Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Grenoble 2) SAS
    Inventors: William Halliday, Eric Saugier, Roy Duffy
  • Publication number: 20200203332
    Abstract: A handshake mechanism allows die discovery in a stacked die architecture that keeps inputs isolated until the handshake is complete. Power good indications are used as handshake signals between the die. A die keeps inputs isolated from above until a power good indication from the die above indicates presence of the die above. The die keeps inputs isolated from below until the die detects power is good and receives a power good indication from the die and the die below. In an implementation drivers and receivers, apart from configuration bus drivers and receivers are disabled until a fuse distribution done signal indicates that repairs have been completed. Drivers are then enabled and after a delay to ensure signals are driven, receivers are deisolated. A top die in the die stack never sees a power good indication from a die above and therefore keeps inputs from above isolated. That allows the height of the die stack to be unknown at power on.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Russell J. Schreiber, Richard M. Born, Carl D. Dietz, William A. Halliday
  • Publication number: 20190369246
    Abstract: A method begins with forming a first wiring layer on a substrate, forming a cavity in the substrate, and laminating a bottom side of the substrate so as to cover a bottom side of the cavity. Next, an integrated circuit is placed within the cavity of the substrate, and then a first optically transparent layer is disposed on the top surface of the substrate to cover a top surface of the integrated circuit. The first optically transparent layer has an aperture formed therein exposing at least a portion of the top surface of the integrated circuit. A second wiring layer is disposed on a top surface of the first optically transparent layer in a pattern that does not obstruct light traveling to or from the top surface of the integrated circuit. The integrated circuit is a laser emitting integrated circuit or a reflected light detector.
    Type: Application
    Filed: August 13, 2019
    Publication date: December 5, 2019
    Applicant: STMicroelectronics (Research & Development) Limited
    Inventor: William HALLIDAY
  • Publication number: 20190316959
    Abstract: An electronic module includes an ambient light sensor and a proximity sensor. The ambient light sensor includes an ambient light photodetector. The proximity sensor includes an infrared photoemitter, a reference infrared photodetector and another infrared photodetector. The ambient light sensor is arranged in a stack over the proximity sensor with a position that allows infrared photons transmitted by the infrared photoemitter to be received by the reference infrared photodetector.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 17, 2019
    Applicants: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Grenoble 2) SAS
    Inventors: William HALLIDAY, Eric SAUGIER, Roy DUFFY
  • Patent number: 10422877
    Abstract: Disclosed herein is an electronic device having a substrate, and an integrated circuit disposed within the substrate and having a top surface. The integrated circuit may be a laser emitting integrated circuit or a reflected light detector. A first interconnect layer is formed on the top surface of the substrate. A first optically transparent layer is formed on the top surface of the substrate and covering the top surface of the integrated circuit. A second interconnect layer is formed on a top surface of the first optically transparent layer. The second interconnect layer is patterned so as to not obstruct light traveling to or from the top surface of the integrated circuit through the first optically transparent layer.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: September 24, 2019
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: William Halliday
  • Patent number: 10261175
    Abstract: A ranging apparatus includes a first array with first light sensitive detectors configured to receive light which has been reflected by an object and generate an output. A second array, spaced apart from the first array by a spacing distance, is further included, the second array having second light sensitive detectors. The second array is configurable to either receive light which has been reflected by the object or to be a reference array and generate an output. A processor operates to determine a distance to the object in response to the outputs from the first and the second arrays.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: April 16, 2019
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: William Halliday
  • Publication number: 20170350981
    Abstract: Disclosed herein is an electronic device having a substrate, and an integrated circuit disposed within the substrate and having a top surface. The integrated circuit may be a laser emitting integrated circuit or a reflected light detector. A first interconnect layer is formed on the top surface of the substrate. A first optically transparent layer is formed on the top surface of the substrate and covering the top surface of the integrated circuit. A second interconnect layer is formed on a top surface of the first optically transparent layer. The second interconnect layer is patterned so as to not obstruct light traveling to or from the top surface of the integrated circuit through the first optically transparent layer.
    Type: Application
    Filed: June 3, 2016
    Publication date: December 7, 2017
    Applicant: STMicroelectronics (Research & Development) Limited
    Inventor: William Halliday
  • Publication number: 20170176577
    Abstract: A ranging apparatus includes a first array with first light sensitive detectors configured to receive light which has been reflected by an object and generate an output. A second array, spaced apart from the first array by a spacing distance, is further included, the second array having second light sensitive detectors. The second array is configurable to either receive light which has been reflected by the object or to be a reference array and generate an output. A processor operates to determine a distance to the object in response to the outputs from the first and the second arrays.
    Type: Application
    Filed: May 11, 2016
    Publication date: June 22, 2017
    Applicant: STMicroelectronics (Research & Development) Limited
    Inventor: William Halliday
  • Patent number: 9413935
    Abstract: A camera module has a lens module mounted on a substrate. The image sensor is located in a cavity in the substrate and is connected to the substrate by a bridge member, the infra-red filter. The image sensor is attached to the infra-red filter by a ring of adhesive surrounding the imaging area of the image sensor. The adhesive attaching the image sensor to the infra-red filter comprises spacers. The infra-red filter is attached to the substrate by adhesive. The cavity may extend through the substrate. The image sensor is further connected to the substrate by a sheet member, which may be made of metal. The sheet member is affixed to the bottom of the substrate and covers the hole in the substrate formed by the extension of the cavity through the substrate. A method of assembly of the camera module includes: providing a substrate with a cavity; locating the image sensor in the cavity; connecting the infra-red filter to the image sensor and the substrate; and mounting the lens module on the substrate.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: August 9, 2016
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: William Halliday
  • Patent number: 9195347
    Abstract: An input device for an electronic device includes a proximity detector and a light source. The light source transmits light to a sensing area, which is reflected back to the proximity detector in the presence of an object in the vicinity of the sensing area, such that the proximity detector can produce an output indicative of a distance of the object from the proximity detector to give rise to a control signal for controlling the device.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: November 24, 2015
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventors: Laurence Stark, William Halliday
  • Patent number: 9099368
    Abstract: A camera module may include a substrate, and an image sensor mounted on the substrate. The camera module may also include a housing, and an electromagnetic interference (EMI) shield provided around the image sensor and within the module. The camera module may be particularly suited for use in a mobile telephone, for example.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: August 4, 2015
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventor: William Halliday
  • Publication number: 20150056588
    Abstract: An Electronic Health Care Coach is provided for patients that have trouble taking their medications or remembering to test for such things as blood sugar and the like. The Electronic Health Care Coach provides voice prompts to the patient to determine compliance with dosing of medications or routine testing. The Electronic Health Care Coach takes the form of a stuffed toy such as a teddy bear and utilizes input sensors that are contained by an appendage of the stuffed toy that are sensitive to human touch. Multiple prompts are employed depending on the responses received. Statistics on patient compliance are collected. The stuffed toy and related voice prompts and input sensors provide a friendly and easy to use reminder system for medications and routine testing that creates a positive experience for the patient, thus increasing patient compliance.
    Type: Application
    Filed: August 21, 2014
    Publication date: February 26, 2015
    Inventor: William Halliday Bayer
  • Patent number: 8906177
    Abstract: A method for controlling a contact angle between a glue and a surface of a substrate during manufacture of microchip packages is disclosed. The method includes applying a glue to a surface of a substrate, and placing an electrode in electrical connection with the glue. A potential difference is applied between the electrode and the substrate. The potential difference is applied across the glue and causes a contact angle between the glue and the surface of the substrate to be altered.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: William Halliday
  • Patent number: 8488056
    Abstract: A camera module includes a substrate with a cavity therein. A processor is located in the cavity, and wire bonding is for connecting the processor to the substrate. An imaging module is adapted to overlay the processor in the cavity and rest on at least part of the edge of the cavity. Wire bonding is for connecting the imaging module to the substrate and the processor. The cavity includes a longitudinal cutout section adapted to accommodate at least some wire bonding for connecting the processor to the substrate or associated surface mount components.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: July 16, 2013
    Assignees: STMicroelectronics (R&D) Ltd., STMicroelectronics Asia Pacific Pte. Limited
    Inventors: William Halliday, Choon Kiat Ooi