Abstract: Detergent compositions and more specifically, to low pH detergent compositions comprising sulfated surfactants, organic acid, and polyamine compounds. Methods of making and using the same.

Abstract: The present invention relates to low pH, compact fluid laundry detergent compositions comprising branched surfactants.

Abstract: Processing within a computing environment that supports pageable guests is facilitated. Processing is facilitated in many ways, including, but not limited to, associating guest and host state information with guest blocks of storage; maintaining the state information in control blocks in host memory; enabling the changing of states; and using the state information in management decisions. In one particular example, the guest state includes an indication of usefulness and importance of memory contents to the guest, and the host state reflects the ease of access to memory contents. The host and guest state information is used in managing memory of the host and/or guests.

Abstract: The present disclosure relates to a storage-stable brightener premix composition, which is substantially free of water and comprises an optical brightener, monoethanolamine, and, optionally, a solvent. The present disclosure also relates to methods of making and using the same.

Abstract: Host page management assist functions are employed to manage storage of a pageable mode virtual environment. These functions enable storage to be managed by a processor of the environment absent intervention of a host of the environment. The functions include a resolve host page function; a pin function; and unpin functions.

Abstract: Embodiments of the invention relate to visiting, by a computing device comprising a processor, each guest of a plurality of guests, obtaining, by the computing device, a list of invalidation counts and revalidation counts associated with resources based on the visiting each guest, and calculating, by the computing device, a target size for invalidating resources for each guest based on the list of invalidation counts and revalidation counts.

Abstract: Processing within a computing environment that supports pageable guests is facilitated. Processing is facilitated in many ways, including, but not limited to, associating guest and host state information with guest blocks of storage; maintaining the state information in control blocks in host memory; enabling the changing of states; and using the state information in management decisions. In one particular example, the guest state includes an indication of usefulness and importance of memory contents to the guest, and the host state reflects the ease of access to memory contents. The host and guest state information is used in managing memory of the host and/or guests.

Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Abstract: Processing within a computing environment that supports pageable guests is facilitated. Processing is facilitated in many ways, including, but not limited to, associating guest and host state information with guest blocks of storage; maintaining the state information in control blocks in host memory; enabling the changing of states; and using the state information in management decisions. In one particular example, the guest state includes an indication of usefulness and importance of memory contents to the guest, and the host state reflects the ease of access to memory contents. The host and guest state information is used in managing memory of the host and/or guests.

Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Abstract: Host page management assist functions are employed to manage storage of a pageable mode virtual environment. These functions enable storage to be managed by a processor of the environment absent intervention of a host of the environment. The functions include a resolve host page function; a pin function; and unpin functions.

Abstract: Host page management assist functions are employed to manage storage of a pageable mode virtual environment. These functions enable storage to be managed by a processor of the environment absent intervention of a host of the environment. The functions include a resolve host page function; a pin function; and unpin functions.

Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Abstract: Aliasing errors, occasioned by, for example, a programming error resulting in including extra or missing bits in a storage address, wrong addressing mode, or wrong address context, are detected by providing a storage address configuration including gaps in valid addresses. Such a programming error is detected and an exception is thrown (that is, an addressing error is detected and indicated) responsive to an address reference to such a gap in valid addresses. Gaps are configured at complementary address ranges to facilitate detection of such aliasing errors.

Abstract: Mapping of address space by providing real storage including first and second address spaces. The second address space is smaller than and contained within the first address space. Provided within virtual storage is a system execution space. Providing within the system execution space is a system execution area having a size equal to or less than the second address space. The system execution area includes a control program having a first portion capable of addressing the first address space and the system execution space, a second portion constrained to address only the second address space and the system execution area, and at least one alias page. Responsive to a control program request for a first page in the virtual storage, a first frame is assigned in real storage corresponding to the page. Responsive to a request from the second portion of the control program for the first page, allocating an alias page in the system execution area, the alias page backed by the first frame.

Abstract: Mapping of address space by providing real storage including first and second address spaces. The second address space is smaller than and contained within the first address space. Provided within virtual storage is a system execution space. Providing within the system execution space is a system execution area having a size equal to or less than the second address space. The system execution area includes a control program having a first portion capable of addressing the first address space and the system execution space, a second portion constrained to address only the second address space and the system execution area, and at least one alias page. Responsive to a control program request for a first page in the virtual storage, a first frame is assigned in real storage corresponding to the page. Responsive to a request from the second portion of the control program for the first page, allocating an alias page in the system execution area, the alias page backed by the first frame.

Abstract: Aliasing errors, occasioned by including extra or missing bits, wrong addressing mode, or wrong address context, are detected by providing a storage configuration including gaps in valid addresses. An exception is thrown responsive to an address reference to a gap. Gaps are configured at complementary address ranges to facilitate detection of aliasing errors.