Abstract: A processer, for example a field programmable gate array (FPGA), comprises input/output (I/O) logic including timing adjustment logic operative to synchronize a time division multiplexed (TDM) line of the I/O logic using an a priori known test pattern. The timing adjustment logic may include clock cycle data alignment logic operative to adjust data on the TDM line by increments of a clock cycle to match it to an a priori known test pattern, and skew logic operative to prevent leading or trailing edges of the data from aligning with edges of a clock pulse leading or trailing edge. The I/O logic may be a Serializer/Deserializer (SerDes) logic that includes a state machine operative to control the clock cycle data alignment logic and skew logic to adjust and synchronize the data with the known test pattern.