Abstract: The present disclosure describes a mechanism for positioning a pair of members in slip-free, adjustable, angular relationships. In accomplishing the foregoing, an assembly is provided which comprises a sphere and a pair of pivotally mounted jaw-like sections for engaging the latter. The inner surfaces of the sections have substantially the same radius of curvature as the sphere surface. Additionally, the sphere surface and the inner surfaces of the jaw-like sections are configured in respective interlocking patterns. Manipulation of the jaw-like sections allows the members to be placed in the desired angular position with respect to each other--which position is maintained by virtue of the aforementioned interlocking nature of the contiguous surfaces.

Abstract: The present invention describes a tester for determining the value of unknown delay lines in the nanosecond and subnanosecond range. The unknown delay line is introduced into the circuit loop of a free-running square wave oscillator previously calibrated to a predetermined frequency. A change in oscillator frequency occurs which is a measure of the value of the delay introduced into the loop by the unknown line. Such delay may be calculated as a function of the calibration and delay line-measured frequencies. The present tester provides measurements with increased accuracy and rapidity over previous measuring techniques.

Abstract: An encoder/decoder is described which allows data transmission on an A.C. coupled transmission system. The encoder converts a serial data stream comprised of combinations of logical "1"'s and "0"'s in an NRZ format to an output pulse train. The latter is characterized not only by phase reversal for each bit of data, as required for A.C. coupled systems, but by bit durations which are dissimilar for a logic "1" and "0". The encoded data is transmitted and subsequently applied to the decoder which restores the data to an NRZ format, and provides a corresponding series of clock pulses for interpreting the data. The encoder/decoder may be implemented in a simple logic configuration.

Abstract: The present disclosure describes a system for substantially eliminating clock signal timing errors occurring between the signal paths of the various cabinets or modules of a large, high speed digital synchronous data processor. Such errors result from the most part because of the long cable lengths needed for coupling the cabinets to a master clock source. The present system provides a measure of the signal delay from the output of the master clock source through the elements of a given cabinet and permits corrective measures to be made at a single location within the cabinet without the necessity of accessing the large number of elements contained therein.

Abstract: The present disclosure describes an improved integrated circuit chip which includes in addition to the logic circuits for performing its design function, an additional circuit for providing a unique reference pattern in digital form useful for test purposes. This reference pattern is automatically read by the tester and gives information as to the type of chip and its final signature. The former indicates to the tester an appropriate test routine such as a pseudo-random binary sequence; and the latter, the predetermined digital pattern which will be present on all of the input and output terminals of a properly functioning integrated circuit chip at the conclusion of the test. Since each chip signature is read by the tester itself, no reference to signatures customarily recorded in tables or inscribed on circuit schematics is required by the test technician.