Abstract: The present invention relates to collapsible cribs. The cribs have one or more of the following characteristics: adjustable length and/or, width and/or height, lightweight, easily collapsed, very compact when collapsed and easily carried, stored and transported. Embodiments disclosed relate to pens, cribs, and play yards with and without wheels.

Abstract: In a network router, a tree structure or a sorting network is used to compare scheduling values and select a packet to be forwarded from an appropriate queue. In the tree structure, each leaf represents the scheduling value of a queue and internal nodes of the structure represent winners in comparisons of scheduling values of sibling nodes of the tree structure. CBR scheduling values may first be compared to select a queue and, if transmission from a CBR queue is not timely, a packet may be selected using WFQ scheduling values. The scheduling values are updated to reflect variable packet lengths and byte stuffing in the prior packet. Scheduling may be performed in multiple stages.

Abstract: A mobile communication device can include a cellular radio-frequency transceiver serviceable by a commercial carrier and a short-range wireless transceiver for communicating with a local access point. The mobile communication device can further include a processor configured to control the operation of the short-range wireless transceiver and the cellular radio-frequency transceiver.

Abstract: A method of task and memory assistance using a mobile communication device can include storing a profile of a user and determining a task to be performed by the user based on the user profile. The method can also include notifying the mobile communication device of the task. The method can further include providing sensory indicators in an increasing order of intervention until an acknowledgement is received from user, or for a predetermined number of notifications.

Abstract: A method of remote surveillance and assisted care using a mobile communication device can include determining a location of a user. The method can also include adjusting at least one camera according to the location, and capturing an image of an area around the location. Further, the method can include transmitting the image to a remote information processing system.

Abstract: In a fabric router, flits are stored on chip in a first set of rapidly accessible flit buffers, and overflow from the first set of flit buffers is stored in a second set of off-chip flit buffers that are accessed more slowly than the first set. The flit buffers may include a buffer pool accessed through a pointer array or a set associative cache. Flow control between network nodes stops the arrival of new flits while transferring flits between the first set of buffers and the second set of buffers.

Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.

Abstract: Compounds of Formula I, 1

Abstract: An SRAM memory cell device comprises wordline and bitline inputs for enabling read/write access to memory cell contents, and, a diffusion region for maintaining a voltage to preserve memory cell content when the cell is not being accessed. The device further comprises a transistor device having a gate input for receiving a wordline voltage to turn off the transistor device when not performing memory cell read/write access; and, a gate oxide layer formed under the transistor device gate exhibiting resistance property for leaking current therethrough when the wordline voltage is applied to the gate input and the transistor device is off. The diffusion region receives voltage derived from the wordline voltage applied to said gate input to enable retention of said memory cell content in the absence of applied bitline voltage to thereby reduce power consumption.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: Disclosed are pyroglutamic acid derivatives and related compounds which bind VLA-4. Certain of these compounds also inhibit leukocyte adhesion and, in particular, leukocyte adhesion mediated by VLA-4. Such compounds are useful in the treatment of inflammatory diseases in a mammalian patient, e.g., human, such as asthma, Alzheimer's disease, atherosclerosis, AIDS dementia, diabetes, inflammatory bowel disease, rheumatoid arthritis, tissue transplantation, tumor metastasis and myocardial ischemia. The compounds can also be administered for the treatment of inflammatory brain diseases such as multiple sclerosis.

Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.

Abstract: A method of forming a liner (and resultant structure) in a contact includes depositing a first layer of refractory metal, annealing the first layer, and sputter depositing a second layer of refractory metal or a compound or an alloy thereof, over the first layer.

Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.

Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.

Abstract: Disclosed are pyroglutamic acid derivatives and related compounds which bind VLA-4. Certain of these compounds also inhibit leukocyte adhesion and, in particular, leukocyte adhesion mediated by VLA-4. Such compounds are useful in the treatment of inflammatory diseases in a mammalian patient, e.g., human, such as asthma, Alzheimer's disease, atherosclerosis, AIDS dementia, diabetes, inflammatory bowel disease, rheumatoid arthritis, tissue transplantation, tumor metastasis and myocardial ischemia. The compounds can also be administered for the treatment of inflammatory brain diseases such as multiple sclerosis.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second substantially horizontal surface at a second depth which is deeper than the first depth. The n- and p-wells are formed on either side of the trench. A highly doped region is formed in the substrate underneath the second substantially horizontal surface of the trench. The highly doped region abuts both the first and the second wells and extends the isolation of the trench.