Patents by Inventor William A. Melton
William A. Melton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20200279590Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.Type: ApplicationFiled: May 18, 2020Publication date: September 3, 2020Inventors: Mahdi Jamali, William A. Melton, Daniele Vimercati, Xinwei Guo, Yasuko Hattori
-
Patent number: 10692547Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.Type: GrantFiled: January 17, 2020Date of Patent: June 23, 2020Assignee: Micron Technology, Inc.Inventors: Mahdi Jamali, William A. Melton, Daniele Vimercati, Xinwei Guo, Yasuko Hattori
-
Publication number: 20200152243Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.Type: ApplicationFiled: January 17, 2020Publication date: May 14, 2020Inventors: Mahdi Jamali, William A. Melton, Daniele Vimercati, Xinwei Guo, Yasuko Hattori
-
Patent number: 10573355Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.Type: GrantFiled: July 16, 2019Date of Patent: February 25, 2020Assignee: Micron Technology, Inc.Inventors: Mahdi Jamali, William A. Melton, Daniele Vimercati, Xinwei Guo, Yasuko Hattori
-
Publication number: 20200013437Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.Type: ApplicationFiled: July 16, 2019Publication date: January 9, 2020Inventors: Mahdi Jamali, William A. Melton, Daniele Vimercati, Xinwei Guo, Yasuko Hattori
-
Patent number: 10395697Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.Type: GrantFiled: February 8, 2018Date of Patent: August 27, 2019Assignee: Micron Technology, Inc.Inventors: Mahdi Jamali, William A. Melton, Daniele Vimercati, Xinwei Guo, Yasuko Hattori
-
Publication number: 20190244641Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.Type: ApplicationFiled: February 8, 2018Publication date: August 8, 2019Inventors: Mahdi Jamali, William A. Melton, Daniele Vimercati, Xinwei Guo, Yasuko Hattori
-
Patent number: 9454427Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.Type: GrantFiled: September 15, 2015Date of Patent: September 27, 2016Assignee: MICRON TECHNOLOGY, INC.Inventors: Aswin Thiruvengadam, Angelo Visconti, Mauro Bonanomi, Richard E. Fackenthal, William Melton
-
Publication number: 20160004595Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.Type: ApplicationFiled: September 15, 2015Publication date: January 7, 2016Inventors: Aswin Thiruvengadam, Angelo Visconti, Mauro Bonanomi, Richard E. Fackenthal, William Melton
-
Patent number: 9176831Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.Type: GrantFiled: February 2, 2015Date of Patent: November 3, 2015Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Angelo Visconti, Mauro Bonanomi, Richard E. Fackenthal, William Melton
-
Patent number: 9082477Abstract: A memory device and method for programming the memory device, including a method for a melting phase change memory cell by applying an electronic signal at a first value and subsequently decreasing the signal value. The phase change memory cell can be substantially crystallized after the decrease in signal value.Type: GrantFiled: May 3, 2013Date of Patent: July 14, 2015Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, William Melton, Rich Fackenthal, Andrew Oen
-
Publication number: 20150149838Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.Type: ApplicationFiled: February 2, 2015Publication date: May 28, 2015Inventors: Aswin Thiruvengadam, Angelo Visconti, Mauro Bonanomi, Richard E. Fackenthal, William Melton
-
Patent number: 8977929Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.Type: GrantFiled: February 27, 2013Date of Patent: March 10, 2015Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Angelo Visconti, Mauro Bonanomi, Richard E. Fackenthal, William Melton
-
Publication number: 20140245107Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Aswin Thiruvengadam, Angelo Visconti, Mauro Bonanomi, Richard E. Fackenthal, William Melton
-
Publication number: 20130242650Abstract: A memory device and method for programming the memory device, including a method for a melting phase change memory cell by applying an electronic signal at a first value and subsequently decreasing the signal value. The phase change memory cell can be substantially crystallized after the decrease in signal value.Type: ApplicationFiled: May 3, 2013Publication date: September 19, 2013Applicant: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, William Melton, Rich Fackenthal, Andrew Oen
-
Patent number: 8441848Abstract: A memory device and method for programming the memory device, more particularly a single pulse algorithm for programming a phase change memory cell or array. The single pulse can heat the memory cell to above its melting point and reduce in signal level so that the memory cell is crystallized.Type: GrantFiled: June 8, 2011Date of Patent: May 14, 2013Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, William Melton, Rich Fackenthal, Andrew Oen
-
Publication number: 20120314491Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a single pulse algorithm for programming a phase change memory.Type: ApplicationFiled: June 8, 2011Publication date: December 13, 2012Applicant: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, William Melton, Rich Fackenthal, Andrew Oen
-
Publication number: 20050250538Abstract: The present invention provides a system, a method and a computer program product for provisioning Virtual PIN pads on mobile devices, and for enabling customers to make payments using the provisioned Virtual PIN pads for the purchased goods and services. The system comprises a Virtual PIN pad and a transaction backend module. The Virtual PIN pad is a software emulation of a PIN Entry Device (PED) and is provisioned on the mobile device securely with all requisite keys and certificates, while conforming to all security standards of the payment domain. The transaction backend connects the Virtual PIN pad to a payment institution. The customer can make a payment by entering an account identifier card's PIN into the Virtual PIN pad. The Virtual PIN pad encrypts the entered PIN using certified security mechanisms, and transmits it over a secure channel to the payment institution for verification and payment authorization, via the transaction backend.Type: ApplicationFiled: May 7, 2004Publication date: November 10, 2005Applicant: JULY SYSTEMS, INC.Inventors: Ashok Narasimhan, Rajesh Reddy, Jyothirmoy Chakravorty, William Melton, Dax Abraham
-
Publication number: 20030167481Abstract: The present invention concerns a method of making a transgenic non-human animal cell which is totipotent or totipotent for nuclear transfer and which cell comprises amplified copies of a nucleic acid sequence of interest. The method comprising subjecting a cell from a host cell population to a gene amplification protocol to produce a cell which retains its totipotency or totipotency for nuclear transfer and which comprises amplified copies of the nucleic acid sequence of interest. Because the resulting cells retain totipotency, or totipotency for nuclear transfer, they may be used to generate a transgenic non-human animal which expresses amplified copies of a gene of interest. Consequently, high levels of a product of interest may be obtained from the animal.Type: ApplicationFiled: March 5, 2003Publication date: September 4, 2003Inventor: David William Melton
-
Patent number: 5175682Abstract: A method and structure are provided for processing checks in an extremely timely and cost-effective manner. A check recipient, such as a merchant, utility billing department, and the like, utilize hardware and software for quickly gathering data from checks received in order to allow prompt processing of those checks. Such hardware preferably includes a reader for reading the MICR account information printed on the check, and means for associating that data with information pertaining to the transaction at hand, including for example, the dollar amount of the transaction. This information is combined in a data record which is stored for future batch data transmission to a clearing house or the issuing bank itself. In an alternative embodiment, this data is communicated in real time to the clearing house or issuing bank. In another embodiment, one or more selection criteria are used to determine which checks will be processed in real time, with the remaining checks being processed in the batch mode.Type: GrantFiled: December 14, 1990Date of Patent: December 29, 1992Assignee: Verifone, Inc.Inventors: Connie Higashiyama, William Melton, Ashok Narasimhan