Abstract: Equipment for treating an annular component of an aircraft turbomachine includes a support of elongate shape along an axis. The support includes, at one of its ends, a mount configured to receive the component, which is intended to extend about the axis. A cover is configured to be mounted on the component and to cover an upstream end of this component. The cover includes an orifice oriented along the axis (X). A clamping member passes through the orifice and is configured to cooperate with the support and to fix the cover to the support. An annular masking gasket extends about the axis and is configured to be interposed between the mount and a downstream end of the component. The gasket has an annular groove configured to be a counter-form of the downstream end.

Abstract: A method provides improved alignment for a photolithographic exposure. In such method, a first exposure tool and a first chuck used in a reference photolithographic exposure of a first material layer on a substrate can be identified. The substrate typically includes at least a semiconductor layer. The first chuck typically is one of a plurality of chucks usable with the first exposure tool. The method may further include identifying a second exposure tool and a second chuck used in a current photolithographic exposure of a second material layer on the substrate. In one embodiment, alignment correction information specific to each of the identified first exposure tool, the first chuck, the second exposure tool and the second chuck can be used in aligning the semiconductor substrate to a second exposure tool and a second chuck.

Abstract: Techniques for estimating a quality of one or more wafers are presented. One or more first wafers comprising one or more first dies are tested. A probability of wafer failure is determined in accordance with one or more first test measurements of the one or more first dies. A pass status and/or a fail status of one or more second wafers is inferred by testing a select one or more second dies of the one or more second wafers and evaluating one or more second test measurements of the select one or more second dies in accordance with the determined probability of wafer failure.

Abstract: A method for fabricating parts using a photolithography system, includes: performing a search of normalization data for an estimated dose operating point; and using the estimated dose operating point for fabrication of new parts.

Abstract: A method provides improved alignment for a photolithographic exposure. In such method, a first exposure tool and a first chuck used in a reference photolithographic exposure of a first material layer on a substrate can be identified. The substrate typically includes at least a semiconductor layer. The first chuck typically is one of a plurality of chucks usable with the first exposure tool. The method may further include identifying a second exposure tool and a second chuck used in a current photolithographic exposure of a second material layer on the substrate. In one embodiment, alignment correction information specific to each of the identified first exposure tool, the first chuck, the second exposure tool and the second chuck can be used in aligning the semiconductor substrate to a second exposure tool and a second chuck.

Abstract: A method of determining positioning error between lithographically produced integrated circuit patterns on at least two different lithographic levels of a semiconductor wafer comprising. The method includes exposing, developing and etching one or more lithographic levels to create one or more groups of marks comprising a target at one or more wafer locations. The method then includes exposing and developing a subsequent group of marks within the target on a subsequent lithographic level. The method then comprises measuring the position of the marks on each level with respect to a common reference point, and using the measured positions of the groups of marks to determine the relative positioning error between one or more pairs of the developed and etched lithographic levels on which the marks are located.

Abstract: Techniques for estimating a quality of one or more wafers are presented. One or more first wafers comprising one or more first dies are tested. A probability of wafer failure is determined in accordance with one or more first test measurements of the one or more first dies. A pass status and/or a fail status of one or more second wafers is inferred by testing a select one or more second dies of the one or more second wafers and evaluating one or more second test measurements of the select one or more second dies in accordance with the determined probability of wafer failure.

Abstract: A method of determining positioning error between lithographically produced integrated circuit patterns on at least two different lithographic levels of a semiconductor wafer comprising. The method includes exposing, developing and etching one or more lithographic levels to create one or more groups of marks comprising a target at one or more wafer locations. The method then includes exposing and developing a subsequent group of marks within the target on a subsequent lithographic level. The method then comprises measuring the position of the marks on each level with respect to a common reference point, and using the measured positions of the groups of marks to determine the relative positioning error between one or more pairs of the developed and etched lithographic levels on which the marks are located.

Abstract: A method for fabricating parts using a photolithography system, includes: performing a search of normalization data for an estimated dose operating point; and using the estimated dose operating point for fabrication of new parts. Other methods are provided.

Abstract: A method of determining overlay error comprises creating a first and second layers of an integrated circuit, each having an active circuit feature and an adjacent kerf area. Each kerf area includes a first measurement feature separated from and corresponding substantially to the layer's active circuit feature. The circuit and kerf areas of the layers are substantially superimposed. The distance of separation between the active circuit feature and the layer kerf measurement feature in each layer in the direction of overlay error is the same. The second layer kerf measurement feature is displaced from the first layer kerf measurement feature in a direction perpendicular to the direction that the overlay error is to be determined. Overlay error is determined by measuring distance of separation in the direction of overlay error between the common points of reference of each of the first and second layer kerf measurement features.

Abstract: A system and method of determining alignment error between lithographically produced integrated circuit fields on the same and different lithographic levels comprises creating a first and second level field layers each having a plurality of integrated circuit fields and associated set of metrology structures adjacent and outside each integrated circuit field. In each level, a metrology structure associated with one integrated circuit field is located to nest with another metrology structure associated with an adjacent circuit field when both are properly aligned on the same lithographic level. Overlay metrology structures are provided on one level to nest with metrology structures of another level when the integrated circuit fields are properly aligned on different lithographic levels.

Abstract: A system and method of determining alignment error between lithographically produced integrated circuit fields on the same and different lithographic levels comprises creating a first and second level field layers each having a plurality of integrated circuit fields and associated set of metrology structures adjacent and outside each integrated circuit field. In each level, a metrology structure associated with one integrated circuit field is located to nest with another metrology structure associated with an adjacent circuit field when the both are properly aligned on the same lithographic level.

Abstract: A method of determining overlay error comprises creating a first and second layers of an integrated circuit, each having an active circuit feature and an adjacent kerf area. Each kerf area includes a first measurement feature separated from and corresponding substantially to the layer's active circuit feature. The circuit and kerf areas of the layers are substantially superimposed. The distance of separation between the active circuit feature and the layer kerf measurement feature in each layer in the direction of overlay error is the same. The second layer kerf measurement feature is displaced from the first layer kerf measurement feature in a direction perpendicular to the direction that the overlay error is to be determined. Overlay error is determined by measuring distance of separation in the direction of overlay error between the common points of reference of each of the first and second layer kerf measurement features.

Abstract: A method of determining bias or overlay error in a substrate formed by a lithographic process uses a pair of straight vernier arrays of parallel elements, a staggered vernier array of parallel elements, and optionally at least one image shortening array on the substrate. The ends of the elements form the array edges. The vernier arrays are overlaid such that: i) the elements of the straight and staggered arrays are substantially parallel; ii) one of the edges of the staggered array intersects with one of the edges of one the straight arrays; and iii) the other of the edges of the staggered array intersects with one of the edges of the other of the straight arrays.

Abstract: A target for determining bias or overlay error in a substrate formed by a lithographic process uses a pair of straight vernier arrays of parallel elements, a staggered vernier array of parallel elements, and optionally at least one image shortening array on the substrate. The ends of the elements form the array edges. The vernier arrays are overlaid such that: i) the elements of the straight and staggered arrays are substantially parallel; ii) one of the edges of the staggered array intersects with one of the edges of one the straight arrays; and iii) the other of the edges of the staggered array intersects with one of the edges of the other of the straight arrays.

Abstract: A support member for an inclined open mesh or wire type shelf that can be spaced anywhere along a wall and shelf area to provide support for the inclined shelf. The support is a one piece molded structure having a T-type cross-section with the shank having curved lower and upper ends with those curves providing about a 60.degree. angle of inclination for the shelf. One end includes a flat surface for engaging the wall with the other end including a forwardly directed groove for receiving a crosswise support in the middle of the shelf and a pair of grooves extending perpendicular to that forwardly directed groove sized so that that end of the support can snap in place between two stringers within the shelf structure.