Abstract: A trans-impedance amplifier arrangement has an input configured to receive an output from a photo-detector, a current monitoring circuit configured in use to provide a current monitor signal dependent on a current through the photo-detector, and an output configured to output said current monitor signal to a control module, said output further configured to receive control information from said control module. A control module is configured to receive the current monitor signal and to provide the control information.

Abstract: In accordance with one or more example embodiments, wireless communications are facilitated based on user-motion. A portable motion-sensing circuit, carried by a user, indicates that motion is sensed in response to detecting whether the user has been moving for a predetermined period of time. A communication circuit operates in active mode and inactive modes respectively consuming higher and lower power, permits or inhibits access authentication communications in the active and inactive modes, and operates in the active mode in response to the motion being sensed at the motion-sensing circuit.

Abstract: In accordance with one or more example embodiments, wireless communications are facilitated based on user-motion. A portable motion-sensing circuit, carried by a user, indicates that motion is sensed in response to detecting whether the user has been moving for a predetermined period of time. A communication circuit operates in active mode and inactive modes respectively consuming higher and lower power, permits or inhibits access authentication communications in the active and inactive modes, and operates in the active mode in response to the motion being sensed at the motion-sensing circuit.

Abstract: A sensing circuit (100) for sensing the content of a memory cell (101), wherein the sensing circuit comprises a sense node (103) connectable to the memory cell (101) so that a signal indicative of the content of the memory cell (101) is providable to the sense node (103). The sensing circuit (100) further comprises a logic gate (102) having a first input, a second input and an output, wherein a reference signal (105) is providable to the first input and wherein the sense node (103) is coupled to the second input. The sensing circuit (100) further comprises a feedback loop (104) for coupling the output of the logic gate (102) to the second input of the logic gate (102) so that, during sensing the content of the memory cell (101), an electrical potential at the sense node (103) is used to make a decision but after a result is obtained, the memory and sense amplifier combination are configured so that the result is held indefinitely and so that no static current continues to flow.

Abstract: The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.

Abstract: A sensing circuit (100) for sensing the content of a memory cell (101), wherein the sensing circuit comprises a sense node (103) connectable to the memory cell (101) so that a signal indicative of the content of the memory cell (101) is providable to the sense node (103). The sensing circuit (100) further comprises a logic gate (102) having a first input, a second in-put and an output, wherein a reference signal (105) is providable to the first input and wherein the sense node (103) is coupled to the second input. The sensing circuit (100) further comprises a feedback loop (104) for coupling the output of the logic gate (102) to the second input of the logic gate (102) so that, during sensing the content of the memory cell (101), an electrical potential at the sense node (103) is used to make a decision but after a result is obtained, the memory and sense amplifier combination are configured so that the result is held indefinitely and so that no static current continues to flow.

Abstract: The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.

Abstract: A method and a receiver for recovering clock timing information from a serial data signal by determining data symbol transition times. The method comprises determining data symbol transition times of the serial data according to a first determination scheme, and further data symbol transition times of the serial data according to a second determination scheme. The transition times are then combined by a voting process, wherein the first determination scheme votes for the transition times that it determined, and wherein the second determination scheme votes for the transition times that it determined. The actual transition times are then determined as being the times that have the most votes.

Abstract: The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.

Abstract: A direct conversion receiver includes a detector that provides a measure of bias offset that is caused by component mismatches in the direct conversion mixer, and a corrective network that reduces the bias offset based on this measure. The direct conversion mixer demodulates a radio-frequency (RF) input signal via mixing with a local-oscillator (LO) signal to provide a differential baseband output signal. A differential peak detector compares the peak signal value at each side of the mixer's differential output, and a differential integrator averages the difference between these peak signal values to provide the measure of bias offset. The corrective network adds a correction offset to each of the local oscillator local oscillator paths on each of the switching pairs that provide the differential output, but opposite to the local oscillator connections.

Abstract: A divide-by-n process is effected via a scale-by-four/n process followed by a divide-by-four process. A quadrature input clock facilitates a scale-by-four/n process, via a clock-phase selection process. By incorporating a terminal divide-by-four process, quadrature output signals are easily provided. A divide-by-three quadrature divider effects the scale-by-4/n process via a selection of every third quadrature clock phase, and the quadrature output of the divide-by-four process provides the control signals to effect this every-third clock phase selection.

Abstract: The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.

Abstract: A variable-impedance device is placed in parallel with the input to a variable-gain amplifier, and is controlled so as to provide a substantially constant load impedance to a source. Preferably, the variable-impedance device includes a diode with a variable bias current. This diode bias current is adjusted inversely with the amplifier bias current, such that the parallel sum of the two input path impedances remains approximately constant across a wide range of gain. This variable gain amplifier system is particularly well suited for use in a wireless transmitter, or cellular telephone.

Abstract: A divide-by-n process is effected via a scale-by-four/n process (110, 210, 310) followed by a divide-by-four process (120, 220, 320). A quadrature input clock facilitates a scale-by-four/n process, via a clock-phase selection process. By incorporating a terminal divide-by-four process, quadrature output signals are easily provided. A divide-by-three quadrature divider effects the scale-by-4/n process via a selection of every third quadrature clock phase, and the quadrature output of the divide-by-four process provides the control signals to effect this every-third clock phase selection.

Abstract: An arrangement for selecting the largest of a plurality of input currents (pma (k?1), pmb (k?1)) and adding a further current (Ibmk) to the selected current, the arrangement comprising: a plurality of inputs (901, 902) for receiving said input currents; a further input (905) for receiving said further current; an output (906, 907) for delivering an output current proportional to the sum of the largest of the input currents and the further current; means for feeding each of the received input currents to the main current conducting path of a respective transistor, (T900, T902) each of the transistors having its control electrode connected to a common point; a respective follower transistor (T901, T903) connected between the input and the common point; and a mirror transistor (T904) having its control electrode connected to the common point for producing a current whose value is related to that of the largest input current.

Abstract: A variable-impedance device is placed in parallel with the input to a variable-gain amplifier, and is controlled so as to provide a substantially constant load impedance to a source. Preferably, the variable-impedance device includes a diode with a variable bias current. This diode bias current is adjusted inversely with the amplifier bias current, such that the parallel sum of the two input path impedances remains approximately constant across a wide range of gain. This variable gain amplifier system is particularly well suited for use in a wireless transmitter, or cellular telephone.

Abstract: An optical disk data decoder generates estimates of serial input signal values by slicing them into samples. The data sequences contained in each sample are detected. Successive samples are compared and used to increase or decrease the estimates. Such permits the center bit in a string of identical bits to be detected after subsequent bits have already been received and are being processed.

Abstract: A low noise amplifier with switchable gain settings comprises a cascoded emitter coupled pair (T1, T2, T5, T6; T3, T4, T7, T8) having a current diverter (T9, T10) which reduces the gain to an intermediate level in response to a control signal on terminals (8, 9). Further control signals on terminals (5, 10, 11, 12, 13) reduce the gain to a low level by introducing emitter degeneration (R3). To compensate for the increase in input impedance caused by the introduction of emitter degeneration feedback loops (C1, R8; C2, R9) are connected between the diversion path and the amplifier inputs.

Abstract: A direct conversion receiver includes a detector that provides a measure of bias offset that is caused by component mismatches in the direct conversion mixer, and a corrective network that reduces the bias offset based on this measure. The direct conversion mixer demodulates a radio-frequency (RF) input signal via mixing with a local-oscillator (LO) signal to provide a differential baseband output signal. A differential peak detector compares the peak signal value at each side of the mixer's differential output, and a differential integrator averages the difference between these peak signal values to provide the measure of bias offset. The corrective network adds a correction offset to each of the local oscillator local oscillator paths on each of the switching pairs that provide the differential output, but opposite to the local oscillator connections.

Abstract: An arrangement for generating an error signal representing the differences between an input signal voltage level (xpk, xnk) and an estimated value (rp, rn) for the input signal voltage level comprises first (T1, T2) and second (T5, T6) transconductors and a differencing circuit (T3, T4, T7, T8) which forms the modulus of the difference between the outputs of the transconductors. The error signal is converted into a probability signal by subtracting the error signal from a constant signal (408) to produce a signal at the output (407) which is a maximum when the input voltage level and estimated voltage level are equal.