Patents by Inventor William A. Shelly

William A. Shelly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11351318
    Abstract: A pressure support device for providing pressure support therapy to a patient includes an airflow generator structured to generate pressure to provide pressure compensation to the patient via a patient circuit, one or more sensors structured to gather data related to effectiveness of the pressure compensation, and a processing unit structured to analyze outputs of the sensors while pressure support therapy is provided to the patient to determine if the pressure compensation provided to the patient is improper and to initiate action to confirm whether components of the patient circuit have been changed in response to determining that the pressure compensation provided to the patient is improper.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 7, 2022
    Assignee: Koninklijke Philips N.V.
    Inventors: Jonathan Sayer Grashow, Benjamin Irwin Shelly, Michael Thomas Kane, Robert William Baiko
  • Patent number: 8569535
    Abstract: The present invention relates to novel compounds of the formula Ia: in any of its stereoisomeric forms or a mixture of stereoisomeric forms in any ratio, or a physiologically acceptable salt thereof, wherein the substituents are as described herein. The inventive compounds have CXCR5 inhibitory activity, and are particularly useful in treating or preventing various inflammatory diseases, such as rheumatoid arthritis, multiple sclerosis, lupus, Crohn's Disease, associated with the modulation of the human CXCR5 receptor.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: October 29, 2013
    Assignee: Sanofi
    Inventors: Thomas Joseph Caulfield, Jennifer Williford Clemens, Robert S. Francis, Brian Scott Freed, Stanly John, Tieu-Binh Le, Brian Pedgrift, Antonio Daniel Ramos, Gerard Charles Rosse, Martin Smrcina, David Squire Thorpe, William Shelly Wire, Jianhong Zhao
  • Patent number: 6970977
    Abstract: In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: November 29, 2005
    Assignee: Bull HN Information Systems Inc.
    Inventors: Wayne R. Buzby, Charles P. Ryan, Robert J. Baryla, William A. Shelly, Lowell D. McCulley
  • Patent number: 6898738
    Abstract: Cache memory, and thus computer system, reliability is increased by duplicating cache tag entries. Each cache tag has a primary entry and a duplicate entry. Then, when cache tags are associatively searched, both the primary and the duplicate entry are compared to the search value. At the same time, they are also parity checked and compared against each other. If a match is made on either the primary entry or the duplicate entry, and that entry does not have a parity error, a cache “hit” is indicated. All single bit cache tag parity errors are detected and compensated for. Almost all multiple bit cache tag parity errors are detected.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: May 24, 2005
    Assignee: Bull HN Information Systems Inc.
    Inventors: Charles P. Ryan, William A. Shelly, Stephen A. Schuerich
  • Publication number: 20040193804
    Abstract: In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Applicant: Bull HN Information Systems Inc.
    Inventors: Wayne R. Buzby, Charles P. Ryan, Robert J. Baryla, William A. Shelly, Lowell D. McCulley
  • Patent number: 6754859
    Abstract: A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.
    Type: Grant
    Filed: January 3, 2001
    Date of Patent: June 22, 2004
    Assignee: Bull HN Information Systems Inc.
    Inventors: Bruce E. Hayden, William A. Shelly
  • Publication number: 20040111656
    Abstract: A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.
    Type: Application
    Filed: October 23, 2003
    Publication date: June 10, 2004
    Inventors: Bruce E. Hayden, William A. Shelly
  • Patent number: 6530076
    Abstract: A processor (92) contains a Trace RAM (210) for tracing internal processor signals and operands. A first trace mode separately traces microcode instruction execution and cache controller execution. Selectable groups of signals are traced from both the cache controller (256) and the arithmetic (AX) processor (260). A second trace mode selectively traces full operand words that result from microcode instruction (242). Each microcode instruction word (242) has a trace enable bit (244) that when enabled causes the results of that microcode instruction (242) to be recorded in the Trace RAM (210).
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: March 4, 2003
    Assignee: Bull HN Information Systems Inc.
    Inventors: Charles P. Ryan, Ron Yoder, William A. Shelly
  • Publication number: 20030018936
    Abstract: Cache memory, and thus computer system, reliability is increased by duplicating cache tag entries. Each cache tag has a primary entry and a duplicate entry. Then, when cache tags are associatively searched, both the primary and the duplicate entry are compared to the search value. At the same time, they are also parity checked and compared against each other. If a match is made on either the primary entry or the duplicate entry, and that entry does not have a parity error, a cache “hit” is indicated. All single bit cache tag parity errors are detected and compensated for. Almost all multiple bit cache tag parity errors are detected.
    Type: Application
    Filed: July 17, 2001
    Publication date: January 23, 2003
    Applicant: Bull NH Information Systems Inc.
    Inventors: Charles P. Ryan, William A. Shelly, Stephen A. Schuerich
  • Patent number: 6484272
    Abstract: In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: November 19, 2002
    Assignee: Bull HN Information Systems, Inc.
    Inventors: David A. Egolf, William A. Shelly, Wayne R. Buzby
  • Patent number: 6480973
    Abstract: In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: November 12, 2002
    Assignee: Bull Information Systems Inc.
    Inventors: William A. Shelly, David A. Egolf, Wayne R. Buzby
  • Publication number: 20020087925
    Abstract: A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.
    Type: Application
    Filed: January 3, 2001
    Publication date: July 4, 2002
    Applicant: Bull HN Information Systems Inc.
    Inventors: Bruce E. Hayden, William A. Shelly
  • Patent number: 6351807
    Abstract: A processor (40) in a data processing system simultaneously loads multiple registers (60) with a single value for fast domain switching. A domain switch instruction asserts a register block write signal (112) along with the register write signal (116) when block writing the single value to the set of registers (60). Register address lines (110, 111) are decoded in two sets: a first set of decoded address lines (110) specifying a block of registers; and the second set (111) specifying one register in the block of registers. When the register block write signal (112) is asserted during a register write, the second set of decoded address lines (111) are ignored, and all registers in the block of registers (60) selected by the first set of decoded address lines (110) are simultaneously loaded with a common value. Additional drive requirements are solved either by adding a buffer (226) to each register bit, or by disabling (228) the feedback path (215) in each register bit during block writes.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: February 26, 2002
    Assignee: Bull HN Information Systems Inc.
    Inventors: Ron W. Yoder, Russell W. Guenthner, William A. Shelly, Eric Earl Conway, Boubaker Shaiek, Claude Rabel
  • Patent number: 6249880
    Abstract: Interactions among multiple processors (92) are exhaustively tested. A master processor (92) retrieves test information for a set of tests from a test table (148). It then enters a series of embedded loops, with one loop for each of the tested processors (92). A cycle delay count for each of the tested processors (92) is incremented (152, 162, 172) through a range specified in the test table entry. For each combination of cycle delay count loop indices, a single test is executed (176). In each such test (176), the master processor (92) sets up (182) each of the other processors (92) being tested. This setup (182) specifies the delay count and the code for that processor (92) to execute. When each processor (92) is setup (182), it waits (192) for a synchronize interrupt (278). When all processors (92) have been setup (182), the master processor (92) issues (191) the synchronize interrupt signal (276). Each processor (92) then starts traces (193) and delays (194) the specified number of cycles.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: June 19, 2001
    Assignee: Bull HN Information Systems Inc.
    Inventors: William A. Shelly, Charles P. Ryan
  • Patent number: 6230263
    Abstract: A processor (92) in a data processing system (80) provides a DELAY instruction. Executing the DELAY instruction causes the processor (92) to a specified integral number of clock (98) cycles before continuing. Delays are guaranteed to have a linear relationship with a constant slope with the specified number of clock cycles. Incrementing the specified delay through a range allows exhaustive testing of interactions among multiple processors.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: May 8, 2001
    Inventors: Charles P. Ryan, Ronald W. Yoder, William A. Shelly
  • Patent number: 6223228
    Abstract: Two instructions are provided to synchronize multiple processors (92) in a data processing system (80). A Transmit Sync instruction (TSYNC) transmits a synchronize processor interrupt (276) to all of the active processors (92) in the system (80). Processors (92) wait for receipt of the synchronize signal (278) by executing a Wait for Sync (WSYNC) instruction. Each of the processors waiting for such a signal (278) is activated at the next clock cycle after receipt of the interrupt signal (278). An optional timeout value is provided to protect against hanging a waiting processor (92) that misses the interrupt (278). Whenever the WSYNC instruction is activated by receipt of the interrupt (278), a trace is started to trace a fixed number of events to an internal Trace Cache (58).
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: April 24, 2001
    Assignee: Bull HN Information Systems Inc.
    Inventors: Charles P. Ryan, William A. Shelly, Ronald W. Yoder
  • Patent number: 6052700
    Abstract: Each processor (92) in a data processing system (80) caches a copy of the master calendar clock (97). The master calendar clock (97) and all of the cached calendar clocks (272) are periodically incremented utilizing a common clock (99). Whenever a processor (92) in the system (80) loads the master calendar clock (97) with a new value, that processor (92) broadcasts a cached calendar clock updated interrupt signal (276) to all of the processors in the system. In response to this interrupt (278), each processor (92) clears its cached calendar clock valid flag (274). Whenever a read calendar clock instruction is executed on a processor (92), the flag (274) is tested, and if set, its cached calendar clock (272) value is returned. Otherwise, the master calendar clock (97) value is retrieved, written to that processor's cached calendar clock (272), and returned. The cached calendar clock valid flag (274) is set to indicate a valid cached calendar clock (272).
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: April 18, 2000
    Assignee: Bull HN Information Systems Inc.
    Inventors: Clinton B. Eckard, William A. Shelly
  • Patent number: 6006309
    Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller including pairs of half-block operand buffers, each divided into quarter block segments. The operand buffer set is coupled to selectively receive, under control of an input multiplexer, requested information blocks from the CPU bus in quarter-block segments and is further coupled to selectively send, under control of an output multiplexer, received quarter-block segments to the CPU and received full blocks to the cache memory.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: December 21, 1999
    Assignee: Bull HN Information Systems Inc.
    Inventors: William A. Shelly, Minoru Inoshita, Robert J. Baryla
  • Patent number: 5963973
    Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: October 5, 1999
    Assignee: Bull HN Information Systems Inc.
    Inventors: Elisabeth Vanhove, Minoru Inoshita, William A. Shelly, Robert J. Baryla
  • Patent number: 5829029
    Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: October 27, 1998
    Assignee: Bull HN Information Systems Inc.
    Inventors: William A. Shelly, Robert J. Baryla, Minoru Inoshita