Abstract: A processing device in a memory sub-system generates a set of media management data associated with a memory device of the memory sub-system. The processing device further causes the set of media management data to be stored in an ultra-high endurance storage class memory device of the memory sub-system.

Abstract: A processing device in a memory sub-system identifies a power loss event associated with the memory sub-system including a memory device and an ultra-high endurance storage class memory device. In response to the power loss event, the processing device further identifies a set of data corresponding to one or more in-flight operations associated with the memory device. The processing device further causes the set of data corresponding to the one or more in-flight operations to be stored in the ultra-high endurance storage class memory device. The processing device further causes execution of a data recovery operation using the set of data corresponding to the one or more in-flight operations to be stored in the ultra-high endurance storage class memory device.

Abstract: A processing device in a memory sub-system receives host data to be stored in a memory sub-system including a memory device and an ultra-high endurance storage class memory device. The processing device further causes the host data to be stored in a host data buffer of the ultra-high endurance storage class memory device. The processing device causes a first portion of the host data stored in the host data buffer to be overwritten during a buffer tenure. In response to determining that a second portion of the host data satisfied a buffer tenure requirement, causing the second portion of the host data to be written from the host data buffer to the primary memory of the memory device.

Abstract: A processing device in a memory sub-system determine that an amount of host data in a portion of an ultra-high endurance storage class memory device configured as a program buffer satisfies a buffer threshold criterion. The processing device further initiates an initial program pass of first host data from the program buffer to a portion of a memory device configured as primary memory and initiates a final program pass of the first host data from the program buffer to the primary memory.

Abstract: A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.

Abstract: A system includes a memory and at least one processing device, operatively coupled to the memory, to perform operations including causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device. The PMR utilizes a power protection mechanism to prevent data loss in an event of power loss.

Abstract: A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.

Abstract: A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

Abstract: A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.

Abstract: A system includes a memory and at least one processing device, operatively coupled to the memory, to perform operations including causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device. The PMR utilizes a power protection mechanism to prevent data loss in an event of power loss.

Abstract: A system includes a first memory device having a region allocated as a first persistent memory region (PMR) having a first set of pages, a second memory device comprising a non-volatile memory device having a region allocated as a second PMR region having a second set of pages, and at least one processing device, operatively coupled to the first memory device and the second memory device, to implement a PMR mechanism to cause the second PMR region to be accessible through the first PMR region.

Abstract: A system includes a first memory device including a non-volatile memory device, a second memory device and a processing device, operatively coupled with the first memory device and the second memory device, to perform operations including configuring a system in accordance with a configuration designating an interface standard for exposing a storage element implemented on the first memory device to a first protocol of the interface standard and a persistent memory region (PMR) implemented on the second memory device to a second protocol of the interface standard, and performing at least one system operation based on the configuration.

Abstract: A request for an estimated temperature of a memory sub-system including multiple components can be received. A set of component temperature values based on temperature measurements at the components can be identified. A subset of the component temperature values can be generated by removing one or more of the component temperature values from the set of component temperature values based on one or more criteria. The estimated temperature value that estimates the temperature of the memory sub-system can be generated using the subset of the component temperature values.

Abstract: A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

Abstract: A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.

Abstract: A method includes detecting an occurrence of an event associated with a memory sub-system comprising blocks of non-volatile memory cells. The method further includes responsive to detecting the occurrence of the event, providing signaling to disable at least a portion of the memory sub-system, an interface coupled to the memory sub-system, or both.

Abstract: A memory component includes multiple fuses, a memory array having a multiple blocks, and control logic operatively coupled with the memory array and the plurality of fuses. The control logic is to perform operations including detecting a failure to completely erase a block of the plurality of blocks in response to an attempted erasure of the block; receiving a blow fuse command in response to the failure to completely erase the block; and blowing a fuse, of the plurality of fuses, coupled with the block, to make the block electrically inaccessible to the control logic in response to receipt of the blow fuse command.

Abstract: A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

Abstract: A system includes a first memory device including a non-volatile memory device, a second memory device and a processing device, operatively coupled with the first memory device and the second memory device, to perform operations including configuring a system in accordance with a configuration designating an interface standard for exposing a storage element implemented on the first memory device to a first protocol of the interface standard and a persistent memory region (PMR) implemented on the second memory device to a second protocol of the interface standard, and performing at least one system operation based on the configuration.

Abstract: A system includes a first memory device having a region allocated as a first persistent memory region (PMR) having a first set of pages, a second memory device comprising a non-volatile memory device having a region allocated as a second PMR region having a second set of pages, and at least one processing device, operatively coupled to the first memory device and the second memory device, to implement a PMR mechanism to cause the second PMR region to be accessible through the first PMR region.