Abstract: In a data synchronizer a timing error estimator samples a received stream of digitized data symbols at the beginning, end, and a mid-point of a symbol period. These samples are used with a model that assumes that a data stream waveform should transition along a straight line between its values at optimum sampling instances, separated by the symbol period. Differences between a mid-symbol sample estimated using this straight line model and the actual mid-symbol sample are assumed to be due to a timing error. The timing error estimator performs computations on complex inputs and therefore is compatible with a wide variety of modulation types.

Abstract: A method and apparatus for performing adaptive filtering in a high interference environment, such as for a radio, modem, or local area network. The adaptive filtering simultaneously provides interference excision while canceling resultant distortion in the signal caused by synthesizing the notch used to excise the interfering signal. An input signal (13) is pre-filtered (14) and the pre-filtered signal (15) is processed by a rejection filter (12) which combines weighted delayed versions of the pre-filtered signal (40, 42, 44, 46, 48, 50), weighted delayed versions of data decisions corresponding to the same delays as that used in the pre-filtered signal (60, 62, 64, 66, 68, 70), and a post filtered signal (27) to produce the filtered signal (19). The filtered signal (19) is processed by a data and coefficient estimator (18) to provide data decisions (25) and tap weight values (21, 23).

Abstract: An apparatus and accompanying method for demodulating with baseband Doppler frequency shift compensation. An RF section (20) down-converts received data communication signals (12) to baseband. A/D converters (24, 26) digitize I, Q quadrature baseband signal components. Phase (32) and frequency (50) tracking loops reside on a common digital ASIC substrate (28). A complex multiplier (30) rotates digitized baseband signals by a digitized oscillation signal, producing Doppler shift compensated signals. The phase tracking loop (32) estimates data and generates a pure phase error signal from which data modulation and Doppler shift compensation influences have been removed, which drives a frequency discriminator (52) that identifies either clockwise or counterclockwise phase rotation for each symbol (18). An integrator (54) combines identification results over a burst and a numerically controlled oscillator (56) adjusts the digitized oscillation signal frequency in a constant frequency step.

Abstract: In a data synchronizer a timing error estimator samples a received data stream and generates a clock to provide optimal sampling of the data stream, and a lock detector monitors the clock and received data stream to provide an indication of whether optimal sampling has been achieved. The lock detector processes differences between delayed versions of the input which are sampled based upon the clock timing. These sampled differences are then processed by a non-linear circuit to provide a lock signal indication which, when compared to a predetermined threshold signal, is used to provide optimal sampling indication. The lock detector performs computations on real and complex inputs and therefore is compatible with a wide variety of modulation types. The lock detector can be implemented in either analog or digital circuits, making it applicable to a broad range of data synchronizer applications.