Abstract: Methods, systems, and devices for tuning a set of simulation parameters associated with a design verification environment are described that include: simulating a circuit design according to a set of simulation parameters; providing, to a machine learning network, an indication of functional coverage results associated with simulating the circuit design according to the set of simulation parameters; receiving an output in response to the machine learning network processing the functional coverage results; and simulating the circuit design based on a recommended set of simulation parameters, wherein simulating the circuit design based on the recommended set of simulation parameters includes generating a set of component signals associated with satisfying a target functional coverage statement. In some aspects, the output includes: the target functional coverage statement associated with the circuit design; and the recommended set of the simulation parameters.

Abstract: Methods, systems, and devices for tuning a set of simulation parameters associated with a design verification environment are described that include: simulating a circuit design according to a set of simulation runs; providing, to a machine learning network, an indication of functional coverage results associated with simulating the circuit design according to the set of simulation runs; receiving an output in response to the machine learning network processing the functional coverage results; and simulating the circuit design based on a recommended set of simulation parameters. The output includes: an indication of a near miss event associated with the functional coverage results; and the recommended set of simulation parameters. Simulating the circuit design based on the recommended set of simulation parameters includes generating a set of component signals associated with triggering the near miss event.

Abstract: A system and a method are disclosed to control flow of victim transactions received at a coherent interconnect from a coherent device of a processing system. A victim transaction is received from the coherent device at the coherent interconnect if a value of a first token indicates that at least one victim transaction is available to be received by the coherent interconnect. A victim transaction is available to be received by the coherent interconnect for each increment of the value of the first token greater than zero. The value of the first token is decremented for each victim transaction received by the coherent interconnect from the coherent device. An indication of the value of the first token is sent to the coherent device from the coherent interconnect.

Abstract: A method and apparatus for partitioning a cache includes determining an allocation of a subcache out of a plurality of subcaches within the cache for association with a compute unit out of a plurality of compute units. Data is processed by the compute unit, and the compute unit evicts a line. The evicted line is written to the subcache associated with the compute unit.

Abstract: A method and apparatus for partitioning a cache includes determining an allocation of a subcache out of a plurality of subcaches within the cache for association with a compute unit out of a plurality of compute units. Data is processed by the compute unit, and the compute unit evicts a line. The evicted line is written to the subcache associated with the compute unit.

Abstract: Techniques for power management in a multi-processor system are disclosed. One of the processors in the system monitors whether all threads on all central processing unit (CPU) cores in the multi-processor system halt, and send a message to a south bridge to cause at least a part of the system to enter a low power state if all threads in the multi-processor system halt. The processor sends another message to the south bridge to cause at least a part of the multi-processor system to wake up if at least one thread on any CPU core in the multi-processor system exits a halt.

Abstract: In one embodiment, a method is contemplated. An interrupt is received in a processor from an interrupt controller. Responsive to receiving the interrupt, the interrupt is masked in the interrupt controller to permit another interrupt to be transmitted by the interrupt controller to the processor. The other interrupt has a lower priority than the previously-received interrupt in the interrupt controller.

Abstract: In one embodiment, an input/output memory management unit (IOMMU) comprises a cache to cache translation data from memory; and a control unit coupled to the cache. The control unit is configured to implement address translation and memory protection for memory requests sourced by one or more input/output (I/O) devices. The memory requests sourced by the I/O devices travel in one or more first virtual channels, and the control unit is configured to transmit memory requests sourced by the control unit in at least a second virtual channel separate from the first virtual channels.

Abstract: A method of routing packets includes receiving a first packet, where the first packet has a first ordering requirement with respect to a prior packet that was received before the first packet, allocating a first entry that corresponds to the first packet in a scheduler, where the first entry includes a first indication of the first ordering requirement, and in response to the first indication, selecting the first entry corresponding to the first packet if one or more first resources used by the first packet and one or more second resources that are used by the prior packet but not by the first packet are available. As long as older entries whose resources are available are selected before newer entries, the first entry will be selected after the prior packet's entry due to the inclusion of the first indication in the first entry.

Abstract: A node includes input ports that are configured to receive packets from other nodes or from devices coupled to the node and output ports that are configured to send packets to other nodes or devices. Scheduling logic may control how packets that are received via the input ports are routed to the output ports. An input port may receive a packet that has multiple destinations or recipients. The scheduling logic may be configured to route this multi-destination packet to at least one of the output ports if at least one of the packet's recipients has an input buffer available to receive the packet.

Abstract: Packets may be routed within a node or a network device using independent input buffers for each interface and a centralized scheduler. By employing a centralized scheduler, the risks of starvation and unfairness may be reduced. Furthermore, a centralized scheduler may be able to track the relative arrival order of all of the packets received by a node or network device, and thus older packets may tend to be routed before younger packets, leading to improved performance. Also, by maintaining independent buffers for each interface, more efficient physical routing may be achieved within a node or network device.

Abstract: An apparatus including circuitry configured to detect and correct an ECC error in a non-targeted portion of a load access to a first data in a memory. An ECC error check circuit is configured to convey a first indication in response to detecting an error in a non-targeted first portion of the first data. A microcode unit is coupled to receive the first indication that the ECC check circuit has detected the ECC error and in response to the indication dispatch a first microcode routine stored by the microcode unit. The first microcode routine includes instructions which, when executed, correct the ECC error in the first portion. Correction of the error in the first portion does not include cancellation of data corresponding to the load access.

Abstract: In a computer system, an address range is defined within the memory map. Addresses within the address range are mapped to other addresses within the memory map using an address relocation mechanism (e.g. the GART mechanism). The address range is divided into two portions. A graphics device may use the first portion to address a contiguous address space, and the addresses are remapped to other address using the address relocation mechanism. Particularly, the contiguous address space used by the graphics device may be remapped to non-contiguous pages elsewhere in the memory map. Other peripheral devices may use the second portion when performing data transfers to portions of the memory map above a predefined limit. The predefined limit may be the highest memory location in the memory map for which the peripheral device is capable of directly generating the address (e.g. 4 GB for a 32 bit address).

Abstract: A partial directory cache records addresses of blocks which are known to be cached in a non-exclusive state in any caches currently caching the blocks. If a read command to a block recorded in the partial directory cache is received, one or more probes corresponding to the command may be inhibited. Since probes are selectively inhibited if an affected block is recorded in the partial directory cache, the size of the partial directory cache may be flexible. If a particular block is not represented in the partial directory cache, probes are performed when the particular block is accessed (even if the particular block could have been represented in the partial directory cache). Thus, coherency is maintained even if every non-exclusively cached block is not represented in the partial directory cache.

Abstract: An apparatus may include an ECC check circuit configured to detect an ECC error in response to an access to first data in a memory and a microcode unit. The microcode unit is coupled to receive an indication that the ECC check circuit has detected the ECC error. In response to the indication, the microcode unit is configured to dispatch a microcode routine stored by the microcode unit. The microcode routine includes instructions which, when executed, correct the ECC error in the memory. In another embodiment, a processor includes the microcode unit and execution circuitry. A method is also contemplated. An access is performed to first data in a memory. An ECC error is detected in response to the access. A microcode routine stored by a microcode unit is dispatched in response to the detecting of the ECC error. The microcode routine includes instructions which, when executed, correct the ECC error in the memory.

Abstract: An apparatus is contemplated, including a router and a memory controller. The router is configured to route a write request and write data to the memory controller. The memory controller is coupled to receive the write request and the write data. If the write data is a number of bytes less than a minimum number of bytes writeable to a memory to which the memory controller is capable of being coupled, the memory controller is configured to read first data from the memory. The first data comprises the minimum number of bytes and includes bytes to be updated with the write data. The memory controller is configured to return the first data to the router as a read response. The router is configured to return the first data to the memory controller.

Abstract: An apparatus is described in which the locations of a buffer are used to store a plurality of control packets received in a node, wherein the plurality of control packets belong to a plurality of virtual channels. The number of locations assigned to each virtual channel may be dynamically allocated. The number of locations allocated to each virtual channel may be determined by an update circuit. Count values corresponding to the number of locations allocated to each virtual channel may then be stored within a programmable storage, such as a register, for example. The count values may be subsequently copied into a slave register and incremented and decremented as locations become available and notifications corresponding to the available locations are sent, respectively.

Abstract: An address relocation cache includes a plurality of entries. Each of the plurality of entries is configured to store at least a portion of an input address, at least a portion of an output address to which the input address translates, and a destination identifier corresponding to the output address. An input address may be translated to the output address and the corresponding destination identifier may be obtained concurrently for input addresses which hit in the address relocation cache. If an input address misses in the address relocation cache, a translation corresponding to the address may be located for storing into the address relocation cache. The output address indicated by the translation may be passed through the address map to obtain the destination identifier, and the destination identifier may be stored in the address relocation cache along with the output address.

Abstract: A processor employing a dependency link file. Upon detection of a load which hits a store for which store data is not available, the processor allocates an entry within the dependency link file for the load. The entry stores a load identifier identifying the load and a store data identifier identifying a source of the store data. The dependency link file monitors results generated by execution units within the processor to detect the store data being provided. The dependency link file then causes the store data to be forwarded as the load data in response to detecting that the store data is provided. The latency from store data being provided to the load data being forwarded may thereby be minimized. Particularly, the load data may be forwarded without requiring that the load memory operation be scheduled.

Abstract: A processor has pre-cache and post-cache buffers. The pre-cache (or LS1) buffer stores memory operations which have not yet probed the data cache. The post-cache (or LS2) buffer stores the memory operations which have probed the data cache. As a memory operation probes the data cache, it is moved from the LS1 buffer to the LS2 buffer. Since misses and stores which have probed the data cache do not reside in the LS1 buffer, the scan logic for selecting memory operations from the LS1 buffer to probe the data cache may be simple and low latency, allowing for the load latency to the data cache for load hits to be relatively low. Furthermore, since the memory operations which have probed the data cache have been removed from the LS1 buffer, the simple scan logic may support high performance features such as allowing hits to proceed under misses, etc.