Abstract: A method for removing damages of a dual damascene structure after plasma etching is disclosed. The method comprises the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure comprising a dual damascene structure that has been treated by the method is disclosed.

Abstract: A method and structure for an integrated via and line lithography followed by integrated via and line etch. A two-layered, negative resist based lithography is used to generate a dual damascene structure in the photoresist which is subsequently transferred into the underlying ILD using an lithography with an integrated RIE. A method is also provided to correct any misalignment between the via and trench during photolithography steps which would reduce the size of the via opening and impact the via resistance.

Abstract: A dual damascene conductor structure is formed on a substrate with an exposed conductor on top covered by a buried cap, a dielectric layer (DL) and an organic layer (OL). Form trench patterning hard mask and via hard mask layers over the OL. Form a trench pattern hole through the via hard mask layer; and form a via pattern hole through the via hard mask layer and the trench hard mask layer. Etch the via pattern hole into the OL and then etch a via pattern hole into the DL. Etch away the trench pattern layer below the trench pattern hole. Etch away the OL layer below the trench pattern hole. Etch the via hole through the DL exposing the cap while simultaneously partially etching the DL to a final trench depth to form a trench into the DL below the trench pattern hole, with the trench having a bottom above the cap and sidewalls in the DL.

Abstract: Method and apparatus for treating an edge region of a wafer. A toroidal shaped plasma cavity has an inner diameter which is slightly less than the diameter of the wafer being treated so that only the edge region of the wafer extends into the toroidal plasma cavity. An inert gas is flowed across a front and back side of the wafer into the plasma cavity. A reactive gas is flowed directly into the plasma cavity. The gases exit the plasma cavity without flowing over the surface of the wafer.

Abstract: Unwanted films can be eliminated by directing a stream of reactive gas(es) at reactive zone in an edge region of the wafer. The action of the reactive gas can be enhanced by heating the gas in a nozzle, immediately prior to the gas impinging on the wafer. The action of the reactive gas can also be enhanced by ultraviolet (UV) or infrared (IR) radiation directed at the reactive zone. The wafer is rotates so that the reactive zone traverses the entire edge region. Multiple gas/light delivery systems can cause gas and light to impinge on multiple reactive zones, both on the front side and on the back side of the wafer.

Abstract: Disclosed is a semiconductor device with a continuously-deposited dielectric layer having different etch resistances through its depth and methods of manufacturing such a device. Specifically, differing etch resistances in the dielectric layer are obtained by modifying the composition of the dielectric layer, the deposition conditions, or both, during deposition of the dielectric layer. The disclosed device and methods eliminate the depth and resistance variations inherent in time-based etch techniques and enable the deposition of a dielectric layer with varying etch resistances in a single deposition step.

Abstract: A method of producing an oxidized tantalum nitride (TaOxNx) hardmask layer for use in dual-damascene processing is described. Fine-line dual-damascene processing places competing, conflicting demands on the hardmask. Whereas critical dimension control needs a thicker hardmask, optical lithographic alignment is frustrated by the opacity of thick tantalum nitride (TaN). The technique solves the problem of TaN hardmask opacity with increasing thickness by oxidizing the TaN layer. Oxidation of the TaN hardmask increases the thickness of the hardmask to two to four times its original thickness and simultaneously increases its transparency by greater than ten times. This permits better CD control associated with a thicker hardmask while facilitating optical lithographic alignment.

Abstract: Interconnect structure having enhanced adhesion between the various interfaces encompassing an organo-silicate glass (OSG) film, for use in semiconductor devices is provided herein. The novel interconnect structure includes a non-damaged plasma-treated low-k OSG surface to enhance the adhesion of the hardmask material to the OSG surface, and an unique deposition scheme for the hardmasks in order to make the entire structure pliant towards implementing mild processing condition during the reactive ion etch patterning of the dielectric structure in a damascene and dual-damascene scheme. The methods for making a semiconductor device having an enhanced adhesion and micromasks free profiles are also provided.

Abstract: A thinned backside illuminated charge-coupled imaging device has improved quantum efficiency by providing a sharp ion implant distribution profile (20) disposed at the rear surface (22) of the device. The sharp ion implant distribution profile (20) is formed using ion implantation at a beam energy potential of between 100-150 keV, which forms an electric field beneath the surface of the device. The ion distribution profile (20) is brought to the surface (22) of the device by removing silicon (18) from the rear surface (22), using a polishing technique wherein the device is lapped with colloidal silica abrasive to controllably remove silicon down to the level of the ion implantation profile (20).

Abstract: A thinned backside illuminated charge-coupled imaging device has improved quantum efficiency by providing a sharp ion implant distribution profile (20) disposed at the rear surface (22) of the device. The sharp ion implant distribution profile (20) is formed using ion implantation at a beam energy potential of between 100-150 keV, which forms an electric field beneath the surface of the device. The ion distribution profile (20) is brought to the surface (22) of the device by removing silicon (18) from the rear surface (22), using a polishing technique wherein the device is lapped with colloidal silica abrasive to controllably remove silicon down to the level of the ion implantation profile (20).

Abstract: A method for fabricating thinned, back-illuminated, solid state image sensors 10 includes steps of positively doping a bottom surface 22 of a top semiconductor wafer 24, and bonding the bottom surface 22 of the top semiconductor wafer 24 to a top surface 26 of a bottom semiconductor wafer 28 with a silicon dioxide passivation layer 34 in between. The top wafer 24 is thinned and an insulating layer of silicon dioxide 36 and a polysilicon gate structure 38 are formed thereover. Individual dies 40 are then formed, which are bonded to a substrate 42 along each pixel face. The bottom semiconductor wafer layer 28 is etched away to expose the silicon dioxide passivation layer 34, which acts to protect the thinned top wafer layer 24. The dies 40 are then etched to expose bonding pads within the gate structure 38, and sized to create thinned, back-illuminated, solid state image sensors 10.

Abstract: A multi-position rotary valve for injecting a variable liquid sample into a stream of diluent flowing through a high pressure liquid chromatograhic column, without interrupting diluent pressure conditions is disclosed. The valve is switchable between a load position and an inject position. Associated with the valve are a plurality of sample loops each of whose upstream ends are selectively connected to a needle cavity in the valve. Moreover the valve possesses means for arcuately articulation whereby one of the loops may be selected from loading of the sample and then for presentation to a diluent under pressure while in each of such position is also in operative alignment with the column.