Abstract: A circuit breaker for a power controller integrated circuit is described where an analog timer and a digital timer are provided in parallel. The digital timer provides a fixed, on-chip maximum delay during an overcurrent condition to ensure the transistor will not be damaged. The analog timer allows the user to select an external capacitor or resistor to provide a delay time that is shorter than the time provided by the digital timer. Accordingly, the power controller retains all the flexibility of an analog timer but prevents the overcurrent exceeding a maximum time limit. An autoretry circuit is also included in the power controller which prevents the duty cycle from exceeding a maximum. The autoretry timer is a digital timer that uses the same oscillator as the digital timer for the circuit breaker so the ratio of the delay times is known and fixed.

Abstract: An accelerator circuit is incorporated in a laser diode system for accelerating the turn-on operation of the laser diode independent of the control loop bandwidth of the laser diode system. The accelerator circuit provides a boost current to a compensation capacitor upon laser turn-on which compensation capacitor operates to establish the control loop bandwidth of the laser diode system. The boost current enables the control loop to increase the bias current to the laser diode quickly. When the laser diode reaches the desired operating point, the boost current is terminated and the control loop of the laser diode system resumes normal control of the bias current. In one embodiment, the accelerator circuit includes a timer circuit controlling a current source to implement open loop turn-on control. In another embodiment, the accelerator circuit includes a comparator circuit working in conjunction with an one-shot logic circuit for providing close loop control.

Abstract: A power budget monitoring circuit in a multi-port PSE includes a differential amplifier and a transistor for setting a reference voltage across a first resistor to establish a reference current, multiple current mirror output devices each associated with a power port of the PSE, a second resistor and a comparator. Each current mirror output device provides an output current indicative of the power demanded by the associated power port where the output currents are summed at a second node into a monitor current. The second resistor has a resistance value proportional to a maximum power budget of the PSE and receives the monitor current. A monitor voltage develops across the second resistor indicative of the total power demanded by the power ports. The comparator compares the monitor voltage to the reference voltage and provides a comparator output signal indicating whether the maximum power budget of the PSE has been exceeded.

Abstract: A power controller system is described herein, which may consist of one or more power controller ICs and other components. Each power controller selectively couples power supply voltages to a plurality of electrical devices, such as cards that have been inserted into expansion slots in a server. To simplify processing by a system processor monitoring the health of the power subsystem, each power controller IC asserts a power-good signal at a power-good terminal only if the operating conditions for all channels are satisfactory. A power good signal is generated even if a channel is not supplying power to a channel due to a card retention switch signal not being asserted or the channel is not enabled. The power-good signals from all power controllers in the system are then ANDed together to determine if any of the power controllers are experiencing unsatisfactory conditions.

Abstract: A power controller system is described herein, where a power-good signal (PWRGD) is asserted followed by a slightly delayed power-good signal (DLY_PWRGD) upon the system powering up. This PWRGD signal indicates that good power is being supplied to the card or other equipment, and the delayed signal tells a system processor that it is now ok to communicate with the card or other equipment. This delay allows the card or other equipment to reach a steady state condition before being declared operational by the power controller. When powering down the equipment, the DLY_PWRGD signal is first deasserted and power is decoupled from the card or other equipment. The PWRGD signal is then deasserted after a short delay. This short delay allows circuitry within the card to be properly shut down by, for example, carrying out a shutdown routine, using stored charge in the card to temporarily power the card. A state machine is used to carry out the four-state power up and power down sequence.

Abstract: An accelerator circuit is incorporated in a laser diode system for accelerating the turn-on operation of the laser diode independent of the control loop bandwidth of the laser diode system. The accelerator circuit provides a boost current to a compensation capacitor upon laser turn-on which compensation capacitor operates to establish the control loop bandwidth of the laser diode system. The boost current enables the control loop to increase the bias current to the laser diode quickly. When the laser diode reaches the desired operating point, the boost current is terminated and the control loop of the laser diode system resumes normal control of the bias current. In one embodiment, the accelerator circuit includes a timer circuit controlling a current source to implement open loop turn-on control. In another embodiment, the accelerator circuit includes a comparator circuit working in conjunction with an one-shot logic circuit for providing close loop control.

Abstract: An accelerator circuit is incorporated in a laser diode system for accelerating the turn-on operation of the laser diode independent of the control loop bandwidth of the laser diode system. The accelerator circuit provides a boost current to a compensation capacitor upon laser turn-on which compensation capacitor operates to establish the control loop bandwidth of the laser diode system. The boost current enables the control loop to increase the bias current to the laser diode quickly. When the laser diode reaches the desired operating point, the boost current is terminated and the control loop of the laser diode system resumes normal control of the bias current. In one embodiment, the accelerator circuit includes a timer circuit controlling a current source to implement open loop turn-on control. In another embodiment, the accelerator circuit includes a comparator circuit working in conjunction with an one-shot logic circuit for providing close loop control.

Abstract: A power budget monitoring circuit in a multi-port PSE includes a differential amplifier and a transistor for setting a reference voltage across a first resistor to establish a reference current, multiple current mirror output devices each associated with a power port of the PSE, a second resistor and a comparator. Each current mirror output device provides an output current indicative of the power demanded by the associated power port where the output currents are summed at a second node into a monitor current. The second resistor has a resistance value proportional to a maximum power budget of the PSE and receives the monitor current. A monitor voltage develops across the second resistor indicative of the total power demanded by the power ports. The comparator compares the monitor voltage to the reference voltage and provides a comparator output signal indicating whether the maximum power budget of the PSE has been exceeded.

Abstract: A power controller system is described herein, where a power-good signal (PWRGD) is asserted followed by a slightly delayed power-good signal (DLY_PWRGD) upon the system powering up. This PWRGD signal indicates that good power is being supplied to the card or other equipment, and the delayed signal tells a system processor that it is now ok to communicate with the card or other equipment. This delay allows the card or other equipment to reach a steady state condition before being declared operational by the power controller. When powering down the equipment, the DLY_PWRGD signal is first deasserted and power is decoupled from the card or other equipment. The PWRGD signal is then deasserted after a short delay. This short delay allows circuitry within the card to be properly shut down by, for example, carrying out a shutdown routine, using stored charge in the card to temporarily power the card. A state machine is used to carry out the four-state power up and power down sequence.

Abstract: A circuit breaker for a power controller integrated circuit is described where an analog timer and a digital timer are provided in parallel. The digital timer provides a fixed, on-chip maximum delay during an overcurrent condition to ensure the transistor will not be damaged. The analog timer allows the user to select an external capacitor or resistor to provide a delay time that is shorter than the time provided by the digital timer. Accordingly, the power controller retains all the flexibility of an analog timer but prevents the overcurrent exceeding a maximum time limit. An autoretry circuit is also included in the power controller which prevents the duty cycle from exceeding a maximum. The autoretry timer is a digital timer that uses the same oscillator as the digital timer for the circuit breaker so the ratio of the delay times is known fixed.

Abstract: A power controller system is described herein, which may consist of one or more power controller ICs and other components. Each power controller selectively couples power supply voltages to a plurality of electrical devices, such as cards that have been inserted into expansion slots in a server. To simplify processing by a system processor monitoring the health of the power subsystem, each power controller IC asserts a power-good signal at a power-good terminal only if the operating conditions for all channels are satisfactory. A power good signal is generated even if a channel is not supplying power to a channel due to a card retention switch signal not being asserted or the channel is not enabled. The power-good signals from all power controllers in the system are then ANDed together to determine if any of the power controllers are experiencing unsatisfactory conditions.

Abstract: A timer circuit includes a current mirror, a capacitor, a first switch, a resistor and a comparator. The current mirror receives a reference current and provides first and second currents with a predefined current ratio. The capacitor receives the first current as a sinking current or as a sourcing current. The first switch, controlled by a control signal, allows the capacitor to be charged by the first current or be discharged. The resistor is biased by the second current to provide an adaptive reference voltage. The comparator compares the voltage across the capacitor and the adaptive reference voltage and triggers an output signal when the capacitor voltage is increased to the adaptive reference voltage.

Abstract: An accelerator circuit is incorporated in a laser diode system for accelerating the turn-on operation of the laser diode independent of the control loop bandwidth of the laser diode system. The accelerator circuit provides a boost current to a compensation capacitor upon laser turn-on which compensation capacitor operates to establish the control loop bandwidth of the laser diode system. The boost current enables the control loop to increase the bias current to the laser diode quickly. When the laser diode reaches the desired operating point, the boost current is terminated and the control loop of the laser diode system resumes normal control of the bias current. In one embodiment, the accelerator circuit includes a timer circuit controlling a current source to implement open loop turn-on control. In another embodiment, the accelerator circuit includes a comparator circuit working in conjunction with an one-shot logic circuit for providing close loop control.

Abstract: A timer circuit includes a current mirror, a capacitor, a first switch, a resistor and a comparator. The current mirror receives a reference current and provides first and second currents with a predefined current ratio. The first switch, controlled by a control signal, allows the capacitor to be charged by the first current or be discharged. The resistor is biased by the second current to provide an adaptive reference voltage. The comparator compares the voltage across the capacitor and the adaptive reference voltage and triggers an output signal when the capacitor voltage is increased to the adaptive reference voltage. Alternately, the timer circuit includes a pin for coupling to an external resistor and an open pin detector circuit to detect the presence of the external resistor and to automatically select the adaptive reference voltage if a resistor is present or an internal reference voltage if the resistor is absent.

Abstract: A control circuit receives complementary logic signals ranging from Vdd to 0 VDC, and outputs a drive signal Vhs1 ranging from magnitude Vhv to Vhv+Vdd to control a high-side switch. The control circuit includes an Ibias generator and a level shift circuit that preferably includes a passive current sink mechanism, coupleable between Vdd and ground. The level shift circuit includes a totem-pole configuration of a PMOS device, an NMOS device, and an NMOS device that mirrors Ibias current. An additional NMOS device is provided, whose source node is coupled between the PMOS and NMOS devices in the totem-pole, whose gate node is coupled to Vdd, and whose drain node serves as an interface to the load circuit. A capacitor coupled across the current source hastens Vhs1 transition time. The PMOS and NMOS devices in the totem pole turn on and off complementarily responsive to the logic signals, which dictate the state of Vhs1.