Abstract: A bullet hit detecting target panel which is configured with at least one calibration trace having a resistance that is set, and/or adjusted, to meet the characteristics of the target panel, such as panel type, zone arrangement and resistance characteristics of the conductive layers. When the target is physically and electrically connected to a target controller, then a calibration procedure is entered by applying a conductor to one or more resistive calibration structures on the target panel. Electrical characteristics of the resistive calibration structures are measured, and used for setting a hit threshold for target zones on the target panel. After which the conductor may be removed and the target is ready to accurately register hits based on the established hit threshold.

Abstract: A method and apparatus for a microprocessor with a cache that has the advantages given by a victim cache without physically having a victim cache is disclosed. In one embodiment, a victim flag may be associated with each way in a set. At eviction time, the way whose victim flag is true may be evicted. However, the victim flag may be reset to false if a superceding request arrives for the cache line in that way. Another cache line in another way may then have its victim flag made true.