Patents by Inventor William B. Barker

William B. Barker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090296525
    Abstract: A method for determining presence of seismic events in seismic signals includes determining presence of at least one seismic event in seismic signals corresponding to each of a plurality of seismic sensors. A correlation window is selected for each of the plurality of seismic signals. Each correlation window has a selected time interval including an arrival time of the at least one seismic event in each seismic signal. Each window is correlated to the respective seismic signal between a first selected time and a second selected time. Presence of at least one other seismic event in the seismic signals from a result of the correlating.
    Type: Application
    Filed: May 27, 2008
    Publication date: December 3, 2009
    Inventors: Leo Eisner, David Abbott, William B. Barker, James Lakings, Michael P. Thornton
  • Patent number: 4130865
    Abstract: Computer apparatus which employs a plurality of processing units, a memory unit, and a communication unit, each of the units including a data transfer bus. A bus coupler is provided between each pair of units of differing type to form a distributed data communications network. An addressable, passive task register is associated with one of the units for communication through the couplers and is adapted to register a task priority value associated with a task request, the register being readable by any one of the processor units to obtain the highest priority value registry.
    Type: Grant
    Filed: October 6, 1975
    Date of Patent: December 19, 1978
    Assignee: Bolt Beranek and Newman Inc.
    Inventors: Frank E. Heart, Severo M. Ornstein, William B. Barker, William R. Crowther
  • Patent number: 4035766
    Abstract: The error-checking scheme disclosed herein is adapted for use in digital data processing systems, e.g. computers, in which binary data is variously transmitted and/or stored and in which the data source or destination is designated by a binary address. In a preferred embodiment, the data is divided into two fields and a respective parity bit is generated corresponding to each data field. Each data parity bit is then combined with a parity bit corresponding to the binary address to yield a respective combinational parity bit. Each of the resultant combinational parity bits is then sourced with the respective data field. Accordingly, a system sub-component receiving the sourced data with the combinational parity bits can detect any type of single error occurring in either the address or the data.
    Type: Grant
    Filed: August 1, 1975
    Date of Patent: July 12, 1977
    Assignee: Bolt, Beranek and Newman, Inc.
    Inventor: William B. Barker