Abstract: One embodiment is a microelectronic assembly including an assembly support structure; a first die including a pair of hot via comprising through-substrate-via (TSVs) extending through the first die between first and second sides thereof and a plurality of ground vias surrounding the pair of hot vias and extending through the first die between the first and second sides thereof. The first die further includes a pair of signal interconnect structures electrically connected to the pair of hot vias disposed on the second side of the first die. The assembly further includes a second die between the assembly support structure and the first die the pair of signal interconnect structures disposed on the first side thereof. The first die is connected to the second die via a signal die-to-die (DTD) interconnect structure including the signal interconnect structures of the first and second dies.

Abstract: A low noise amplifier topology can achieve very low noise figure by applying multiple magnetic coupling between gate matching inductors and source degeneration inductor of a field effect transistor. The resulting low noise amplifier has smaller inductors, which can have lower thermal noise contribution, and can maintain good gain and linearity performance. For example, a low noise amplifier includes a first inductor to receive an input; a second inductor coupled to the first inductor in series; a first field effect transistor device whose gate receives a signal from the second inductor; and a third inductor coupled to a source of the first field effect transistor device, where the third inductor is magnetically positively coupled to the first inductor and the second inductor.

Abstract: One embodiment is a microelectronic assembly including an assembly support structure; a first die including a pair of hot via comprising through-substrate-via (TSVs) extending through the first die between first and second sides thereof and a plurality of ground vias surrounding the pair of hot vias and extending through the first die between the first and second sides thereof. The first die further includes a pair of signal interconnect structures electrically connected to the pair of hot vias disposed on the second side of the first die. The assembly further includes a second die between the assembly support structure and the first die the pair of signal interconnect structures disposed on the first side thereof. The first die is connected to the second die via a signal die-to-die (DTD) interconnect structure including the signal interconnect structures of the first and second dies.

Abstract: Miniature slow-wave transmission lines are described having an asymmetrical ground configuration. In some embodiments, the asymmetrical ground configuration facilitates a reduction in size. Non-uniform auxiliary conductors may be disposed above or below the co-planar waveguide to facilitate a reduction in the length of the miniature slow-wave transmission lines. Phase shifters may be implemented having a reduced size by including one or more miniature slow-wave transmission lines.

Abstract: An electrical circuit can be formed at least in part using lumped or discrete circuit elements to provide an artificial transmission line structure that can mimic the electrical properties of a corresponding actual transmission line structure. Such an artificial transmission line structure can generally consume less area than an actual transmission line structure lacking such lumped or discrete elements. Such an artificial transmission line structure can be formed using two or more “unit cells” such as by cascading such cells as shown and described herein. The present inventors have recognized, among other things, that a unit cell of an artificial transmission line structure can include a t-coil section comprising magnetically-coupled inductors. Such an artificial transmission line structure can be used for applications such as phase shifting or to provide a delay line having a substantially constant group delay, among other applications.

Abstract: An electrical circuit can be formed at least in part using lumped or discrete circuit elements to provide an artificial transmission line structure that can mimic the electrical properties of a corresponding actual transmission line structure. Such an artificial transmission line structure can generally consume less area than an actual transmission line structure lac0ure can be formed using two or more “unit cells” such as by cascading such cells as shown and described herein. The present inventors have recognized, among other things, that a unit cell of an artificial transmission line structure can include a t-coil section comprising magnetically-coupled inductors. Such an artificial transmission line structure can be used for applications such as phase shifting or to provide a delay line having a substantially constant group delay, among other applications.

Abstract: An electronic circuit can include a gain adjustment circuit (e.g., a gain “equalizer” circuit), such as to compensate for a variation in insertion loss over a specified range of frequencies. For example, such a gain adjustment circuit can provide an insertion loss characteristic having a specified slope. Such a slope can include a positive slope where insertion loss increases with respect to frequency, or a negative slope where insertion loss decreases with respect to frequency, as illustrative examples. A gain equalization technique can be used to compensate for variation in insertion loss versus frequency between different circuit paths, such as in relation to a switchable delay line having two or more selectable paths, such as for phase shifting applications. A gain adjustment circuit can be configured to provide relatively flat or constant time-domain delay versus frequency, such as inhibiting or reducing dispersion.

Abstract: Miniature slow-wave transmission lines are described having an asymmetrical ground configuration. In some embodiments, the asymmetrical ground configuration facilitates a reduction in size. Non-uniform auxiliary conductors may be disposed above or below the co-planar waveguide to facilitate a reduction in the length of the miniature slow-wave transmission lines. Phase shifters may be implemented having a reduced size by including one or more miniature slow-wave transmission lines.

Abstract: A power divider/combiner circuit with coupled inductors is provided. With coupled inductors, the new circuit topology exhibits broader bandwidth for insertion loss, port matching and isolation compared with traditional power divider/combiner circuit topologies. The coupled inductors can be implemented for single-stage low-pass networks, multi-stage low-pass networks, or multi-stage wide-band networks. For example, the power divider/combiner circuit includes a first coupled inductor circuit coupled to an input terminal that provides a first signal path to a first output terminal, and a second coupled inductor circuit coupled to the input terminal that provides a second signal path to a second output terminal. Each of the coupled inductor circuits include multiple inductors that are tightly and positively magnetically coupled to one another.

Abstract: A power divider/combiner circuit with coupled inductors is provided. With coupled inductors, the new circuit topology exhibits broader bandwidth for insertion loss, port matching and isolation compared with traditional power divider/combiner circuit topologies. The coupled inductors can be implemented for single-stage low-pass networks, multi-stage low-pass networks, or multi-stage wide-band networks. For example, the power divider/combiner circuit includes a first coupled inductor circuit coupled to an input terminal that provides a first signal path to a first output terminal, and a second coupled inductor circuit coupled to the input terminal that provides a second signal path to a second output terminal. Each of the coupled inductor circuits include multiple inductors that are tightly and positively magnetically coupled to one another.

Abstract: A double-balanced FET mixer may include: single-ended RF port that receives or delivers single-ended RF signal; RF balun that converts the received single-ended RF signal into differential RF signal or generates delivered single-ended RF signal from received differential RF signal; local oscillator input port receives local oscillator signal; direct IF port receives or delivers an IF signal; and at least two FETs process the local oscillator signal and generate or process the differential RF signal and IF signal. The mixer may have no IF balun separate and distinct from tRF balun; may receive an input signal at RF port and generates output signal at IF port. The mixer may receive input signal at IF port and generate an output signal at the RF port, the output signal in either case being plus or minus the local oscillator signal. The double-balanced FET mixer may operate with IF frequencies down to DC.

Abstract: A double-balanced FET mixer may include: single-ended RF port that receives or delivers single-ended RF signal; RF balun that converts the received single-ended RF signal into differential RF signal or generates delivered single-ended RF signal from received differential RF signal; local oscillator input port receives local oscillator signal; direct IF port receives or delivers an IF signal; and at least two FETs process the local oscillator signal and generate or process the differential RF signal and IF signal. The mixer may have no IF balun separate and distinct from tRF balun; may receive an input signal at RF port and generates output signal at IF port. The mixer may receive input signal at IF port and generate an output signal at the RF port, the output signal in either case being plus or minus the local oscillator signal. The double-balanced FET mixer may operate with IF frequencies down to DC.

Abstract: A broadband radio frequency, microwave, or millimeter mixer system may include a balun and a mixer. The balun may have an unbalanced port; a balanced port; a first and a second inductor tightly and inversely magnetically coupled to one another; and a third inductor which is not magnetically coupled to the first or the second inductors. The mixer may be connected to the balanced port of the balun. The balun, including its three inductors, and the mixer may all be integrated onto a single substrate that forms an integrated circuit.

Abstract: A broadband radio frequency, microwave, or millimeter mixer system may include a balun and a mixer. The balun may have an unbalanced port; a balanced port; a first and a second inductor tightly and inversely magnetically coupled to one another; and a third inductor which is not magnetically coupled to the first or the second inductors. The mixer may be connected to the balanced port of the balun. The balun, including its three inductors, and the mixer may all be integrated onto a single substrate that forms an integrated circuit.

Abstract: Frequency conversion circuitry has an input node for receiving an input signal at a first frequency and an output node for producing an output signal at a second frequency different from the first frequency. A mixer circuit is responsive to the input signal for producing a signal at the second frequency. A step down impedance transformation circuit is coupled between the input node and an input of the mixer circuit for providing input impedance of the mixer circuit lower than impedance at the input node. An amplifier circuit is coupled between an output of the mixer circuit and the output node for amplifying the signal at the second frequency produced at the output of the mixer circuit. The mixer circuit is configured for providing input impedance of the output amplifier lower than the impedance at the input node.

Abstract: A power amplifier (50) includes two transistors (11, 21) and a dynamic biasing circuit (52). The dynamic biasing circuit (52) uses a sampling circuit (54) to generate a bias adjusting signal proportional to the amplitude of an AC signal at a drain electrode of the first transistor (11). The bias adjusting signal is combined with a constant voltage bias signal to generate a dynamic biasing signal applied to a gate electrode of the second transistor (21). As the gain of the first transistor (11) decreases, the amplitude of the AC signal at its drain electrode decreases. Thus, the dynamic biasing circuit (52) generates a lower dynamic biasing signal at the gate electrode of the second transistor (21), thereby decreasing a quiescent drain current in the second transistor (21) and improving the efficiency of the amplifier (50) at low output power levels.

Abstract: An attenuator circuit uses single point control to adjust the attenuation levels between first and second nodes. The attenuator is set-up as a .pi.-network with a pass transistor and first and second shunt transistors. Capacitors are coupled in the drain and source conduction paths of the first and second shunt transistors for DC isolation to float the shunt transistors. A control voltage applied at the drain of the pass transistor and the gates of the first and second shunt transistors controls the attenuation level. A parallel resistor and capacitor combination at the drain of the first shunt transistor provides tuning to match the input impedance of the attenuator to the sourcing circuit.

Abstract: A signal mixing apparatus comprising first and second four port signal splitting/combining networks having no relative phase shift between three ports and 180.degree. of phase shift between the remaining ports, coupled to a four port mixer element. The mixer element has two ports coupled to the first signal splitter/combiner network and having another two ports coupled to the second splitter/combiner, RF and LO signals input to the first splitter/combiner do not appear at the IF output from the second splitter/combiner or vice versa. The RF/IF signals cancel and the LO signal is trapped by a resonant circuit within the mixer. The RF and IF frequency bands may overlap.

Abstract: A method and apparatus for improved isolation of IF, LO, and RF frequency signals from the non-associated mixer ports (e.g., avoiding introducing RF frequency signals at the IF and LO ports, and similarly vis-a-vis other signals and ports), is provided by coupling a RF (or LO) signal to first ports of four-port first and second phase shift means, each having two signal output ports having 180.degree. phase difference for signals input from the first port, coupling the LO (or RF) signal to the first port of a third phase shift means, with two output signal ports having a phase difference of 180.degree., supplying the third phase shift means output signals to fourth ports of the first and second phase shift means, supplying the output signals of the first and second phase shift means to distinct ports of a five port mixer, and coupling an IF signal from the five port mixer to an IF port.

Abstract: A N-stage differential distributed amplifier arrangement. The differential distributed amplifier arrangement includes a parallel connection of N-differential amplifiers. The inputs to the amplifiers are delayed so that the same input is received by each amplifier in sequence at a slightly later time than the preceding amplifier. The outputs of each amplifier are also delayed so that the output of the previous amplifier is added to the output of the next sequential amplifier. Thereby the output is an amplified version of the input. By appropriate grounding of inputs or outputs the differential distributed amplifier arrangement may convert from balanced signals to single-ended signals, from single-ended signals to balanced signals or from two inputs to two outputs.