Abstract: Methods, systems, and devices for staggered horizontal cell architecture for memory devices are described. Generally, the described techniques provide for a memory device that supports staggered cell architectures and techniques to manufacture the memory device. The memory device may include a stack of materials including alternating layers of dielectric and conductive material. The memory device may include one or more staircase structures coupled with the stack of layers. The memory device may include access lines, such as bit lines, that are staggered according to a pattern, such as a serpentine pattern of dielectric fill surrounding the access lines. The memory device may include a set of repeatable structures that may be interlaced in a staggered configuration. The repeatable structure may include two fins extending in opposite directions and coupled to a respective staircase structure.

Abstract: Compounds and compositions comprising epoxyeicosatrienoic acid (EET) analogs that act as EET agonists and are useful as medications in the treatment of drug-induced nephrotoxicity, hypertension and other related conditions. Methods of making and using the compounds and compositions are further described.

Abstract: Compounds and compositions comprising epoxyeicosatrienoic acid (EET) analogs that act as EET agonists and are useful as medications in the treatment of drug-induced nephrotoxicity, hypertension and other related conditions. Methods of making and using the compounds and compositions are further described.

Abstract: Compounds and compositions comprising epoxyeicosatrienoic acid (EET) analogs that act as EET agonists and are useful as medications in the treatment of drug-induced nephrotoxicity, hypertension and other related conditions. Methods of making and using the compounds and compositions are further described.

Abstract: In one embodiment, an apparatus is described. The apparatus includes an input/output (I/O) device that is capable of being coupled to a computing system. The device is configured such that, in operation, the I/O device has the capability to interrupt an associated computing system processor based at least in part on a comparison of a threshold value with the quantity of transmit resources available to the I/O device.

Abstract: Numerous embodiments of a method and apparatus for avoiding an out of resource condition are disclosed.