Abstract: A thermoelectric device includes a plurality of thin-film thermoelectric elements. Each thin-film thermoelectric element is a Seebeck-Peltier device. The thin-film thermoelectric elements are electrically coupled in parallel with each other. The thermoelectric device may be fabricated using conventional semiconductor processing technologies and may be a thin-film type device.

Abstract: A thermoelectric device includes a plurality of thin-film thermoelectric elements. Each thin-film thermoelectric element is a Seebeck-Peltier device. The thin-film thermoelectric elements are electrically coupled in parallel with each other. The thermoelectric device may be fabricated using conventional semiconductor processing technologies and may be a thin-film type device.

Abstract: A self-aligned polysilicon gate depletion-type n-channel IGFET serving as a load transistor in a mesa-type integrated circuit having a P+ field region surface. The gate is ring-shaped and surrounds the IGFET source region. The source region does not intersect a mesa edge. The gate overlaps mesa edges to reduce peripheral capacitance.

Abstract: A method of making a ROM and encoding it late in the method. Encoding is by ion implantation. A second level of polycrystalline used for resistors outside the ROM is used as the encoding mask.

Abstract: An IGFET ROM is programmed late in its process of manufacture. An array of IGFETs having an operable channel region and gate electrode is provided. The gate electrode is penetrable by an ion beam. A first dielectric penetrable by the ion beam is deposited onto the array. A second dielectric not penetrable by the ion beam is then deposited onto the array. Windows are then etched into the second dielectric material but not the first, over channel regions of selected IGFETs. The wafer surface is given an ion implantation to change threshold voltage of those IGFETs selected. A metallization pattern is formed on the second dielectric, with the first dielectric providing an insulating coating for gate electrode portions otherwise exposed within the aforementioned windows.

Abstract: A method of making a ROM and encoding it late in the method. A silicon nitride layer etch mask is used for encoding by ion implantation, avoiding the need for a separate encoding mask.

Abstract: A method of making a high speed and high density IGFET read-only memory and encoding it late in said method. A unique ROM structure permits encoding by ion implantation thin apertures in a phosphosilicate glass layer, without requiring ROM output lines passing over the implant apertures or expanding ROM size to obtain highest ROM operating speed.

Abstract: A method of making a ROM and a two-level polycrystalline silicon RAM on a chip and encoding the ROM in later stages of the method, without adding a mask to the method. The mask used to define the second level of polycrystalline silicon for the RAM is also used to provide an ion implant mask for the ROM.

Abstract: Windows in a glass coating on a semiconductor wafer surface are opened to an underlying semiconductor device region without inadvertently exposing adjacent device portions within the window. In the preferred process a precisely etchable silicon nitride coating is initially applied and windows precisely etched in it. The glass is applied later and preferentially etched, whereby undesired lateral etching of the glass can occur without unintentionally exposing adjacent device portions.

Abstract: An IGFET ROM is programmed later in its process of manufacture. An array of IGFETs having an operable channel region and gate electrode is provided. The gate electrode is penetrable by an ion beam. A first dielectric penetrable by the ion beam is deposited onto the array. A second dielectric not penetrable by the ion beam is then deposited onto the array. Windows are then etched into the second dielectric material but not the first, over channel regions of selected IGFETs. The wafer surface is given an ion implantation to change threshold voltage of those IGFETs selected. A metallization pattern is formed on the second dielectric, with the first dielectric providing an insulating coating for gate electrode portions otherwise exposed within the aforementioned windows.