Abstract: Electronic component protection power supply clamp circuits comprising a plurality of p-type channel metal-oxide-semiconductor (PMOS) and n-type channel metal-oxide-semiconductor (NMOS) transistors are described. These clamp circuits use a feedback latching circuit to retain an electrostatic discharge (ESD)-triggered state and efficiently conduct ESD current that has been diverted into the power supply, in order to dissipate ESD energy. The feedback latching circuit also maintains a clamp transistor in its off state if the clamp circuit powers up untriggered, thus enhancing the clamp circuit's immunity to noise during normal operation. Passive resistance initialization of key nodes to an untriggered state, as well as passive resistance gate input loading of a large ESD clamping transistor, further enhances the clamp circuit's immunity to false triggering.

Abstract: Electronic component protection power supply clamp circuits comprising a plurality of p-type channel metal-oxide-semiconductor (PMOS) and n-type channel metal-oxide-semiconductor (NMOS) transistors are described. These clamp circuits use a feedback latching circuit to retain an electrostatic discharge (ESD)-triggered state and efficiently conduct ESD current that has been diverted into the power supply, in order to dissipate ESD energy. The feedback latching circuit also maintains a clamp transistor in its off state if the clamp circuit powers up untriggered, thus enhancing the clamp circuit's immunity to noise during normal operation. Passive resistance initialization of key nodes to an untriggered state, as well as passive resistance gate input loading of a large ESD clamping transistor, further enhances the clamp circuit's immunity to false triggering.

Abstract: Electronic component protection power supply clamp circuits comprising a plurality of p-type channel metal-oxide-semiconductor (PMOS) and n-type channel metal-oxide-semiconductor (NMOS) transistors are described. These clamp circuits use a feedback latching circuit to retain an electrostatic discharge (ESD)-triggered state and efficiently conduct ESD current that has been diverted into the power supply, in order to dissipate ESD energy. The feedback latching circuit also maintains a clamp transistor in its off state if the clamp circuit powers up untriggered, thus enhancing the clamp circuit's immunity to noise during normal operation. Passive resistance initialization of key nodes to an untriggered state, as well as passive resistance gate input loading of a large ESD clamping transistor, further enhances the clamp circuit's immunity to false triggering.

Abstract: A method and apparatus for generating a reference voltage potential, also known as an input switching reference, using differential clock signals or other differential signals that ideally have a 180 degree phase shift is provided. The differential signals are generated by a transmitting circuit. The reference voltage potential is dependent on the differential signals. The voltage potentials of the differential signals are averaged and low-pass filtered. Comparators in a receiving circuit compare an input signal's voltage potential to the reference voltage potential to determine if the transmitted input signal is a binary one or binary zero.

Abstract: A bi-directional input/output (IO) cell for transmitting and receiving data signals simultaneously over a single line. The bidirectional IO cell having an IO node adapted to connect to the line. A driver has an output connected to the line and an input for receiving a core output signal. A first differential amplifier has a first input connected to the IO node and a second input connected to a high voltage reference circuit. A second differential amplifier has a first input connected to the IO node and a second input connected to a low voltage reference circuit.

Abstract: A method and apparatus for generating a reference voltage potential, also known as an input switching reference, using differential clock signals or other differential signals that ideally have a 180 degree phase shift is provided. The differential signals are generated by a transmitting circuit. The reference voltage potential is dependent on the differential signals. The voltage potentials of the differential signals are averaged and low-pass filtered. Comparators in a receiving circuit compare an input signal's voltage potential to the reference voltage potential to determine if the transmitted input signal is a binary one or binary zero.

Abstract: A bi-directional input/output (IO) cell for transmitting and receiving data signals simultaneously over a single line. The bidirectional IO cell having an IO node adapted to connect to the line. A driver has an output connected to the line and an input for receiving a core output signal. A first differential amplifier has a first input connected to the IO node and a second input connected to a high voltage reference circuit. A second differential amplifier has a first input connected to the IO node and a second input connected to a low voltage reference circuit.

Abstract: A present invention discloses an automated method to generate an eye-plot for signals produced by a simulation or captured hardware results. The automated approach is customizable in that the designer may specify input parameters to customize the analysis to fit the needs of the user. The eye-plot is then generated. The eye-plot may be output on the printer, displayed on the video display or even stored in secondary storage for subsequent review and use.

Abstract: An apparatus and method are provided for damping a noise component of a power signal from a power source. The apparatus and method are able to produce a load current in phase with the noise component to lower an effective impedance of a circuit driven by the power source to damp the noise component. The apparatus and method are able to produce the load current in phase with the noise component between a first cutoff frequency and a second cutoff frequency. The first cutoff frequency is determined in part by a time constant and the second cutoff frequency is determined in part by the physical properties of the materials that form the apparatus.

Abstract: An analysis facility analyzes simulation output resulting from a simulator of an electrical component, such as a microprocessor. The simulation output contains waveform representations of at least one data signal and a clock signal. The analysis facility analyzes the waveform representations and the simulation output to produce a report regarding signaling performance metrics, such as data jitter, setup times and hold times. The analysis facility may be customized by the user specifying parameters. For example, the user may specify what portion of the time frame for which simulation results produced are to be analyzed by the analysis facility. The user may also specify parameters such as cycle time and reference voltage values, including an indeterminate state region.

Abstract: A synchronous interconnect structure is provided for transmitting and receiving source synchronous signals. The receiver of the synchronous interconnect structure continuously monitors the phase relationship between the source clock signal and each transmitted data signal. In this manner, the synchronous interconnect structure can perform signal timing alignment for each transmitted clock and data signal in near real time fashion without impacting data transmission rates across the synchronous interconnect structure.

Abstract: An electronic apparatus for receiving source synchronous signals is provided. The receiver continuously monitors the phase relationship between each data signal and the source synchronous clock signal. In this manner, the electronic apparatus can compensate for phase discrepancies that occur over time without having to interrupt any data operations.

Abstract: A circuit for limiting voltage transient excursions on a power supply node is disclosed. The circuit includes a first field effect transistor dispose to provide a capacitance and having source and drain electrodes coupled to said external supply node path and having a gate electrode and first and second clamp transistors. A resistance is coupled between the gate electrode of said first transistor and the internal supply return node and to gate electrodes of the clamp transistors. The circuit also include process resistances between internal and external supply connection to provide a charge transfer path between external and internal supply nodes and external and internal return nodes.

Abstract: A circuit for limiting voltage transient excursions on a power supply node is disclosed. The circuit includes a first field effect transistor dispose to provide a capacitance and having source and drain electrodes coupled to said external supply node path and having a gate electrode and first and second clamp transistors. A resistance is coupled between the gate electrode of said first transistor and the internal supply return node and to gate electrodes of the clamp transistors. The circuit also include process resistances between internal and external supply connection to provide a charge transfer path between external and internal supply nodes and external and internal return nodes.

Abstract: A circuit for limiting voltage transient excursions on a power supply node is disclosed. The circuit includes a first field effect transistor dispose to provide a capacitance and having source and drain electrodes coupled to said external supply node path and having a gate electrode and first and second clamp transistors. A resistance is coupled between the gate electrode of said first transistor and the internal supply return node and to gate electrodes of the clamp transistors. The circuit also include process resistances between internal and external supply connection to provide a charge transfer path between external and internal supply nodes and external and internal return nodes.

Abstract: An I/O bus into the cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination Circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.