Patents by Inventor William B. Noyce

William B. Noyce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5764947
    Abstract: A jacketing system automatically interfaces dissimilar program units during program execution on a computer system. Means are provided for detecting a call for execution of a second program unit having a second call standard form a first program unit having a first call standard during execution of the first program unit on the computer system. A procedure descriptor is used in the code for the first program unit and it includes a signature that defines the call standard for each incoming call to the first program unit. A bound procedure descriptor is also used in the code for each outgoing call from the first program unit and it includes a signature that defines the call standard for the target program unit. Jacketing routines are driven by the descriptors in jacketing calls between the two program units.
    Type: Grant
    Filed: March 2, 1994
    Date of Patent: June 9, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Daniel L. Murphy, William B. Noyce
  • Patent number: 5564118
    Abstract: A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
    Type: Grant
    Filed: December 8, 1994
    Date of Patent: October 8, 1996
    Assignee: Digital Equipment Corporation
    Inventors: Simon C. Steely, Jr., David J. Sager, William B. Noyce
  • Patent number: 5481723
    Abstract: A system and method for controlling execution of nested loops in parallel in a computer including multiple processors, and a compiler for generating code therefor. The code enables the computer to operate in the following manner. Each processor processes an iteration of an outer loop in a set of nested loops. If the outer loop contains more iterations than processors in the system, the processors are initially assigned early iterations, and the later iterations are assigned to the processors as they finish their earlier iterations, until the processors have processed all of the iterations. Each processor, during processing of an outer loop iteration runs the iterations comprising the inner loop serially. In order to enforce dependencies between the loops, each processor reports its progress in its iterations of the inner loop to the processor executing the succeeding outer loop iteration.
    Type: Grant
    Filed: February 27, 1995
    Date of Patent: January 2, 1996
    Assignee: Digital Equipment Corporation
    Inventors: Kevin W. Harris, William B. Noyce
  • Patent number: 5339428
    Abstract: A compiler includes a register allocation method making use of the concept of assigning temporary items to lifetime holes if such holes exist that are suitable. The compiler includes a front end for converting the input code to an intermediate representation, then this input representation is traversed to identify all of the temporary items, and to find all of the holes in the temporary items. Lists are maintained of the identified temporaries and holes. Register allocation then includes assigning temporaries to registers so long as there are free registers, and if holes are available in already-assigned temporaries then these holes are used in assigning registers. After all the available registers and holes are used, remaining temporaries are unallocated and thus represent memory references.
    Type: Grant
    Filed: September 4, 1991
    Date of Patent: August 16, 1994
    Assignee: Digital Equipment Corporation
    Inventors: Curt K. Burmeister, Kevin W. Harris, William B. Noyce, Steven O. Hobbs