Abstract: An integrated circuit with improved performance may include conventional integrated circuit layers including at least one integrated circuit power layer; an insulator material layer with a lattice structure deposited across the conventional integrated circuit layers; a first graphene layer deposited on the insulator material layer, wherein the first graphene layer is patterned and etched, allowing edges of the graphene to be in contact with the at least one integrated circuit power layer; a dielectric layer deposited on the first graphene layer; a second graphene layer deposited on the dielectric layer; and a top passivation layer deposited on the second graphene layer.

Abstract: An integrated circuit with improved performance includes conventional integrated circuit layers including at least one integrated circuit power layer; an insulator material layer with a lattice structure deposited across the conventional integrated circuit layers; a first graphene layer deposited on the insulator material layer; a dielectric layer deposited on the first graphene layer; a second graphene layer deposited on the dielectric layer; a top passivation layer deposited on the second graphene layer; a first metallization post extending from the first graphene layer to the at least one integrated circuit power layer; and a second metallization post extending from the second graphene layer to the at least one integrated circuit power layer.

Abstract: The addressable memory space within the retrievable capacity of the microprocessor is necessarily limited by the bit length of the address word. This in turn, is limited by the bit length of the word which the microprocessor may compute or manipulate. By appropriate organization of multiple registers, an extended or expanded memory space may be achieved without the necessity of increasing the word length of the digital information manipulated by the microprocessor. In addition, the microprocessor can be fabricated to be capable of both eight bit and sixteen bit operation by appropriate organization and coordination of a plurality of register files. By virtue of this register file organization and coordination additional improved operations may be achieved, such as direct coupling by the microprocessor between the memory and separate dedicated data processing chips, simplified string instructions and the condensation of entire classes of instructions into single generic instruction formats.