Abstract: Circuits, methods, and apparatus that combine a bus hold and a pull-up circuit in a die area efficient and conflict free manner. An exemplary embodiment of the present invention combines a bus hold resistor with a pull-up resistor. The resistor is connected between a pad and an inverter. When a user selects a bus hold function for the pad, the inverter is enabled and driven through a second inverting gate by the pad. When a pull-up function is selected, the inverter output is driven high. If neither function is selected, the inverter output is tri-stated. In this way, the die area of a second resistor is saved and potential conflicts between these alternately available functions are avoided.

Abstract: A system for generating voltages on an integrated circuit utilizes an overlapping clocking scheme. An oscillator generates the overlapping clock signals, which are coupled through oscillator buffers, to row pumps. In response to the overlapping clock signals, row pumps generate high voltages, typically higher than the VDD voltage of the integrated circuit. These high voltages may be used to program programmable memory cells or interface to logic components of the integrated circuit.

Abstract: An output buffer comprising control circuit for reducing the amount of ground and/or power bounce noise. The output buffer further includes one or more driver devices. The output current of the driver device(s) is limited by providing an intermediate drive voltage to the control electrode of the driver device. A pass device (or a transmission gate) provides the intermediate drive voltage and also operates as a variable resistive device that limits the slew rate of the drive voltage. The operation of the pass device can be dependent on a signal level at the output of the output buffer. When the output has transitioned to a new logic state, the new logic level is fed back to change the operating state of the pass device, thus ensuring that the output voltage meets the output VOL and VOH specifications.

Abstract: A system for generating voltages on an integrated circuit utilizes an overlapping clocking scheme. An oscillator (220) generates the overlapping clock signals, which are coupled through oscillator buffers (225), to row pumps (230). In response to the overlapping clock signals, row pumps (230) generate high voltages, typically higher than the VDD voltage of the integrated circuit. These high voltages may be used to program programmable memory cells or interface to logic components of the integrated circuit.

Abstract: A high voltage pump with an initiation scheme to achieve voltages above VDD. In response to a pulse signal, an initiation voltage is placed on a first node (515) of a voltage pump to initiate pumping action. The initiation voltage is passed through a transistor (545) coupled between a high voltage output node (415) and the first node (515) of the voltage pump. The first node (515) is coupled through a capacitor (510) to an oscillator (405) which charges the first node (515). A high voltage is produced at the high voltage output node (415). The initiation scheme may be applied to one-stage and multiple-stage voltage pumps.