Abstract: An apparatus and a method to inhibit sputtering of undesirable material on to a dielectric layer of an integrated circuit being etched. After exposing the integrated circuit within its package, the leads of the integrated circuit are electrically coupled together by a metallic foil. The metallic foil is wrapped about the package to also provide thermal coupling, however, the integrated circuit is left exposed. Then, the integrated circuit is placed onto an etch-resilient plate disposed atop a cathode electrode. An opening in the plate allows direct placement of the integrated circuit onto the cathode. An etch-resilient cover is placed above the plate opening and the integrated circuit, but the cover has an opening to expose the integrated circuit. During etching, the cover inhibits sputtering from the leads, preform and bond wires.

Abstract: An apparatus and a method to inhibit sputtering of undesirable material onto a dielectric layer of an integrated circuit being etched. After exposing the integrated circuit within its package, the leads of the integrated circuit are electrically coupled together by a metallic foil. The metallic foil is wrapped about the package to also provide thermal coupling, however, the integrated circuit is left exposed. Then, the integrated circuit is placed onto an etch-resilient plate disposed atop a cathode electrode. An opening in the plate allows direct placement of the integrated circuit onto the cathode. An etch-resilient cover is placed above the plate opening and the integrated circuit, but the cover has an opening to expose the integrated circuit. During etching, the cover inhibits sputtering from the leads, preform and bond wires.

Abstract: MOS process for forming field-effect devices in self-alignment with a buried oxide region. Oxygen is implanted in alignment with masking members after gates have been defined from the masking members. The masking members block the oxygen implantation and thus the channel regions of subsequently formed transistors are self-aligned with openings in the buried oxide layer.

Abstract: Improved processing for MOS and CMOS transistors formed in an epitaxial-like layer. Field oxide regions are formed followed by the deposition of a polycrystalline or amorphous silicon layer which contacts the substrate at "seed windows" formed between the field oxide regions. The silicon layer is recrystallized from the substrate through the seed windows. The transistors are fabricated within the recrystallized silicon layer.